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AMD-8131

更新时间： 2024-10-27 23:30:15

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AMD-8131 - AMD-8131 HyperTransport PCI-X Tunnel Data Sheet

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AMD-8131 数据手册

24637 Rev 3.01 - April 04, 2003

AMD-8131^TMPCI-X Tunnel Data Sheet

Cover page

Preliminary AMD-8131^TMHyperTransport^TMPCI-X Tunnel

Data Sheet

Overview

The AMD-8131^TMHyperTransport^TMPCI-X Tunnel (referred to as the IC in this document) is a

HyperTransport™ technology (referred to as link in this document) tunnel developed by AMD that provides

two PCI-X bridges.

1.1 Device Features

•

HyperTransport technology tunnel with side A

and side B.

•

Two PCI-X (rev. 1.0) bridges: bridge A and

bridge B.

•

Side A is 16 bits (input and output); side B is

8 bits.

Either side may connect to the host or to a

downstream HyperTransport technology

compliant device.

Each side supports HyperTransport technol-

ogy-defined reduced bit widths: 8-bit, 4-bit,

and 2-bit.

Each side supports transfer rates of 1600,

1200, 800, and 400 mega-transfers per sec-

ond.

Maximum bandwidth is 6.4 gigabytes per

second across side A (half upstream and half

downstream) and 3.2 gigabytes per second

across side B.

Independent transfer rate and bit width

selection for each side.

•

Each bridge supports a 64-bit data bus.

Each bridge supports operational modes of

PCI-X and legacy PCI revision 2.2 protocol.

Bridges support 133, 100, and 66 MHz

transfer rates in PCI-X mode.

Bridges support 66 and 33 MHz transfer

rates in PCI mode.

Independent transfer rates and operational

modes for each bridge.

Each bridge includes support for up to 5 PCI

masters with clock, request, and grant sig-

nals.

Each bridge includes an IOAPIC with four

redirection registers. Legacy interrupt con-

troller and IOAPIC modes supported.

SHPC-compliant hot plug controller and

support.

•

Link disconnect protocol supported.

•

37.5 x 37.5 millimeter, 829-pin BGA package.

3.3 volt PCI-X signaling; 1.2 volt link signaling;

1.8 volt core.

AMD-8131^TMDevice

Side A Side B

HyperTransport^TM

Link

16 bits upstream,

HyperTransport

Link

8 bits upstream,

Host

Downstream

Device

tunnel

16 bits downstream

8 bits downstream

PCI-X

Bridge A

PCI-X

Bridge B

slots

Figure 1: System block diagram.

12 3 4 5 6 7...80

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