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AMB0480A5BJG

更新时间: 2024-11-26 21:03:19
品牌 Logo 应用领域
艾迪悌 - IDT 内存集成电路
页数 文件大小 规格书
15页 252K
描述
Memory Circuit

AMB0480A5BJG 技术参数

生命周期:ActiveReach Compliance Code:compliant
HTS代码:8542.32.00.71风险等级:5.62
内存集成电路类型:MEMORY CIRCUITBase Number Matches:1

AMB0480A5BJG 数据手册

 浏览型号AMB0480A5BJG的Datasheet PDF文件第2页浏览型号AMB0480A5BJG的Datasheet PDF文件第3页浏览型号AMB0480A5BJG的Datasheet PDF文件第4页浏览型号AMB0480A5BJG的Datasheet PDF文件第5页浏览型号AMB0480A5BJG的Datasheet PDF文件第6页浏览型号AMB0480A5BJG的Datasheet PDF文件第7页 
IDTAMB0480  
PRODUCT  
BRIEF  
ADVANCED MEMORY BUFFER  
FOR FULLY BUFFERED DIMM  
MODULES  
FEATURES:  
DESCRIPTION:  
Advanced Memory Buffer for Fully buffered DIMMs  
3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)  
Support for up to eight DIMMs per channel  
Repeater Mode for extending FB-DIMM links  
The fully buffered dual in-line memory module (FB-DIMM) is the next  
generationmemoryarchitecturetomeetthegrowingmemoryrequirementof  
serversandworkstations.TheIDTAdvancedMemoryBuffer(AMB)chipisthe  
essential building block located on each FB-DIMM. The IDT AMB receives  
Northbound and Southbound single lane fail over and channel commandsanddatafromthehostcontrollertocontrolandwrite/readdatato/  
error detection  
fromtheDRAMsontheDIMM.Commandsandwritedataaresentsouthbound  
fromthehostcontrollertoAMBsinadaisychainfashionandinterpretedbythe  
targetAMB.StatusandreaddataaresentnorthboundfromAMBstothehost  
controlleralsoinadaisychainfashion,passingthroughnon-targetAMBs.This  
uniquechannelstructurealleviatesbufferloadingissuescommoninregistered  
DIMMtechnology,enablingdesignerstousealargenumberofDIMMswithin  
asinglesystem.  
IDTAMB0480complieswiththelatest JEDECdefinedFB-DIMMArchitecture  
andProtocolSpecificationand supportsDDR2-533andDDR2-667DRAM.  
It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480  
supportsservers,workstations,storagedevicesandcommunicationapplications  
thatsupportthenextgenerationFB-DIMMarchitecture.  
Voltage and Timing margin high-speed I/O test capability  
Fully Supports the FB-DIMM configuration register set  
Test features supported include:  
- Integrated thermal sensor and status indicator  
- Supports MEMBIST, IBIST and Virtual Host mode  
- Transparent mode and direct access mode for DRAM testing  
Complies with JEDEC Architecture and Protocol Specification  
Available in 655 ball FCBGA package  
EXPANDEDFEATURES:  
Wide range DDR Timing Control  
• Superfine adjustment for DDR timing  
Wide range of DDR slew rate control  
• Slew rate controllable independent of output impedance  
High speed SMBus in test mode  
IBIST IDT PRBS Generator  
FDBMEMORYCHANNEL  
Up to 8 modules  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
14  
Host  
IDT  
AMB  
IDT  
AMB  
IDT  
AMB  
IDT  
AMB  
Memory  
Controller  
10  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
DDR2  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
APRIL 2006  
1
c
2006 Integrated Device Technology, Inc.  
DSC - 7042/2  

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