Datasheet > AM79C978AKCW

AM79C978AKCW

更新时间： 2024-01-27 17:48:50

品牌	Logo	应用领域
超微 - AMD		外围集成电路数据传输控制器 PC 局域网时钟
页数	文件大小	规格书
256页	3313K
描述
Single-Chip 1/10 Mbps PCI Home Networking Controller

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AM79C978AKCW 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP, QFP144,.87SQ,20
针数：	144	Reach Compliance Code：	compliant
HTS代码：	8542.31.00.01	地址总线宽度：	32
边界扫描：	YES	总线兼容性：	PCI
最大时钟频率：	33.33 MHz	数据编码/解码方法：	BIPH-LEVEL(MANCHESTER)
最大数据传输速率：	1.25 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
长度：	20 mm	低功率模式：	YES
串行 I/O 数：	5	端子数量：	144
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装等效代码：	QFP144,.87SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.6 mm
子类别：	Serial IO/Communication Controllers	最大供电电压：	3.63 V
最小供电电压：	2.97 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	20 mm
uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN	Base Number Matches：	1

AM79C978AKCW 数据手册

Am79C978A

PCnet™- Home

Single-Chip 1/10 Mbps PCI Home Networking Controller

DISTINCTIVE CHARACTERISTICS

n Fully integrated 1 Mbps HomePNA Physical Layer

(PHY) as defined by Home Phoneline Networking

Alliance (HomePNA) specification 1.1

— Big endian and little endian byte

alignments supported

— Implements optional PCI power management

— Optimized for home networking applications

event (PME) pin

over ordinary copper telephone wire

n Dual-speed CSMA/CD (10 Mbps and 100 Mbps)

Media Access Controller (MAC) compliant with

IEEE/ANSI 802.3 Ethernet standard

— In-band control features

n Adjustable power and speed levels

n Compliant with HomePNA specification 1.1

n 32 bits of reserved in-band messaging

piggybacked on Ethernet packet

n Media Independent Interface (MII) for

connecting external 10/100 Mbps transceivers

— Register programmable features

n Power control

— IEEE 802.3u compliant MII

— Intelligent Auto-Poll™ external PHY status

n Performance registers

n Speed control

monitor and interrupt

— Supports both auto-negotiable and non-

n Major frame timing parameters programmable:

auto-negotiable external PHYs

ISBI, AID ISBI, pulse width, inter-symbol time

— Supports 10BASE-T, 100BASETX/FX,

100BASET4, and 100BASET2 IEEE 802.3

compliant MII PHYs at full-duplex or half-

duplex

n Fully integrated 10 Mbps PHY interface

— Comprehensive Auto-Negotiation

implementation

— Full-duplex capability

n Full-duplex operation supported on the MII port

with independent Transmit (TX) and Receive

(RX) channels

— Optimized for 10BASE-T applications

n Integrated Fast Ethernet controller for the

Peripheral Component Interconnect (PCI) bus

n Supports PC98/PC99 and Net PC specifications

— 32-bit glueless PCI host interface

— Implements full OnNow features including

pattern matching and link status wake-up

events

— Supports PCI clock frequency from DC to

33 MHz independent of network clock

— Supports network operation with PCI clock

— Implements Magic Packet™ mode

from 15 MHz to 33 MHz

— Magic Packet mode and the physical address

loaded from EEPROM at power up without

requiring PCI clock

— High performance bus mastering

architecture with integrated Direct Memory

Access (DMA) Buffer Management Unit for

low CPU and bus utilization

— Supports PCI Bus Power Management

Interface specification revision 1.1

— PCI draft specification revision 2.2 compliant

— Supports Advanced Configuration and Power

— Supports PCI Subsystem/Subvendor ID/

Vendor ID programming through the

EEPROM interface

Interface (ACPI) specification version 1.0

— Supports Network Device Class Power

Management specification version 1.0a

— Supports both PCI 5.0-V and 3.3-V

n Independent internal TX and RX FIFOs

signaling environments

— Programmable FIFO watermarks for both TX

— Plug and Play compatible

and RX operations

— Supports an unlimited PCI burst length

Publication# 22399 Rev: C Amendment/0

Issue Date: January 2000

Refer to AMD’s Website (www.amd.com) for the latest information.

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