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AM6411BSCGHAALV

更新时间： 2024-11-20 11:07:07
品牌 Logo 应用领域
德州仪器 - TI PC
页数 文件大小 规格书
237页 5006K
描述
单核 64 位 Arm® Cortex®-A53，单核 Cortex-R5F，具有 PCIe、USB 3.0 和安全性 | ALV | 441 | -40 to 105

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AM6411BSCGHAALV 数据手册

 浏览型号AM6411BSCGHAALV的Datasheet PDF文件第2页浏览型号AM6411BSCGHAALV的Datasheet PDF文件第3页浏览型号AM6411BSCGHAALV的Datasheet PDF文件第4页浏览型号AM6411BSCGHAALV的Datasheet PDF文件第5页浏览型号AM6411BSCGHAALV的Datasheet PDF文件第6页浏览型号AM6411BSCGHAALV的Datasheet PDF文件第7页 
AM6442, AM6441, AM6421  
AM6412, AM6411  
SPRSP56 – JANUARY 2021  
AM64x Sitara™ Processors  
•
Two 64-bit Industrial Ethernet Peripherals  
(IEPs) for time stamping and other time  
synchronization functions  
1 Features  
Processor cores:  
•
18× Sigma-Delta filters  
– Short circuit logic  
•
1× Dual 64-bit Arm® Cortex®-A53 microprocessor  
subsystem at up to 1.0 GHz  
– Over-current logic  
– Dual-core Cortex-A53 cluster with 256KB L2  
shared cache with SECDED ECC  
– Each A53 Core has 32KB L1 DCache with  
SECDED ECC and 32KB L1 ICache with Parity  
protection  
2× Dual-core Arm® Cortex®-R5F MCU subsystems  
at at up to 800 MHz, integrated for real-time  
processing  
•
•
•
6× Multi-protocol position encoder interfaces  
One Enhanced Capture Module (ECAP)  
16550-compatible UART with a dedicated  
192-MHz clock to support 12-Mbps  
PROFIBUS  
•
Memory subsystem:  
– Dual-core Arm® Cortex®-R5F supports dual-  
•
Up to 2MB of On-chip RAM (OCSRAM) with  
SECDED ECC:  
core and single-core modes  
– Can be divided into smaller banks in  
increments of 256KB for as many as 8 separate  
memory banks  
– Each memory bank can be allocated to a single  
core to facilitate software task partitioning  
DDR Subsystem (DDRSS)  
– 32KB ICache, 32KB DCache and 64KB TCM  
per each R5F core for a total of 256KB TCM  
with SECDED ECC on all memories  
1× Single-core Arm® Cortex®-M4F MCU at up to  
400 MHz  
•
•
•
– 256KB SRAM with SECDED ECC  
– Supports LPDDR4, DDR4 memory types  
– 16-Bit data bus with inline ECC  
Industrial subsystem:  
•
2× gigabit Industrial Communication Subsystems  
(PRU_ICSSG)  
– Supports Profinet IRT, Profinet RT, EtherNet/IP,  
EtherCAT, Time-Sensitive Networking (TSN),  
and more  
– Supports speeds up to 1600 MT/s  
1× General-Purpose Memory Controller (GPMC)  
– 16-Bit parallel bus with 133 MHz clock or  
– 32-Bit parallel bus with 100 MHz clock  
– Error Location Module (ELM) support  
– Backward compatibility with 10/100Mb  
PRU_ICSS  
System on Chip (SoC) Services:  
– Each PRU_ICSSG contains:  
•
Device Management Security Controller (DMSC-L)  
– Centralized SoC system controller  
– Manages system services including initial boot,  
security, and clock/reset/power management  
– Communication with various processing units  
over message manager  
•
•
2× 10/100/1000 Ethernet ports  
6 PRU RISC cores per PRU_ICSSG each  
core having:  
– Instruction RAM with ECC  
– Broadside RAM  
– Multiplier with optional accumulator  
(MAC)  
– Simplified interface for optimizing unused  
peripherals  
– CRC16/32 hardware accelerator  
– Byte swap for Big/Little Endian  
conversion  
– SUM32 hardware accelerator for UDP  
checksum  
– Task Manager for preemption support  
Three Data RAMs with ECC  
8 banks of 30 × 32-bit register scratchpad  
memory  
•
Data Movement Subsystem (DMSS)  
– Block Copy DMA (BCDMA)  
– Packet DMA (PKTDMA)  
– Secure Proxy (SEC_PROXY)  
– Ring Accelerator (RINGACC)  
•
•
Security:  
•
Secure boot supported  
– Hardware-enforced Root-of-Trust (RoT)  
– Support to switch RoT via backup key  
•
Interrupt controller and task manager  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change  
without notice.  
 
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