PRELIMINARY
Am42DL32x4G
Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 4 Mbit (256 K x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
SOFTWARE FEATURES
MCP Features
■ Power supply voltage of 2.7 to 3.3 volt
■ Data Management Software (DMS)
—
AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
Eases sector erase limitations
■ High performance
—
—
Flash Access time as fast as 70 ns
Pseudo SRAM access time as fast as 55 ns
—
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
■ Package
—
73-Ball FBGA
—
Suspends erase operations to allow programming in same
bank
■ Operating Temperature
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–40°C to +85°C
■ Data# Polling and Toggle Bits
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Provides a software method of detecting the status of
program or erase cycles
Flash Memory Features
■ Unlock Bypass Program command
ARCHITECTURAL ADVANTAGES
—
Reduces overall programming time when issuing multiple
program command sequences
■ Simultaneous Read/Write operations
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Data can be continuously read from one bank while
executing erase/program functions in other bank
Zero latency between read and write operations
HARDWARE FEATURES
—
■ Any combination of sectors can be erased
■ Secured Silicon (SecSi) Sector: Extra 256 Byte sector
■ Ready/Busy# output (RY/BY#)
—
Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
Customer lockable: Sector is one-time programmable. Once
locked, data cannot be changed
—
Hardware method for detecting program or erase cycle
completion
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■ Hardware reset pin (RESET#)
—
Hardware method of resetting the internal state machine to
reading array data
■ Zero Power Operation
Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
—
■ WP#/ACC input pin
—
Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
■ Top or bottom boot block
—
Acceleration (ACC) function accelerates program timing
■ Manufactured on 0.17 µm process technology
■ Compatible with JEDEC standards
■ Sector protection
—
Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
—
Pinout and software compatible with single-power-supply
flash standard
—
Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
■ High performance
—
—
Access time as fast as 70 ns
Pseudo SRAM Features
■ Power dissipation
Program time: 4 µs/word typical utilizing Accelerate function
■ Ultra low power consumption (typical values)
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Operating: 22 mA maximum for 70 ns, 30 mA maximum for
—
—
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2 mA active read current at 1 MHz
55 ns
10 mA active read current at 5 MHz
200 nA in standby or automatic sleep mode
—
Standby: 10 µA maximum
■ CE1s# and CE2s Chip Select
■ Minimum 1 million write cycles guaranteed per sector
■ 20 Year data retention at 125°C
■ Power down features using CE1s# and CE2s
■ Data retention supply voltage: 1.5 to 3.3 volt
■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
—
Reliable operation for the life of the system
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 25822 Rev: A Amendment/+4
Issue Date: March 14, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.