AM3874, AM3871
www.ti.com
SPRS695B –SEPTEMBER 2011–REVISED SEPTEMBER 2012
AM387x Sitara™
ARM® Processors
Check for Samples: AM3874, AM3871
1 High-Performance System-on-Chip (SoC)
1.1 Features
12
– Two 165 MHz HD Video Display Outputs
One 16/24/30-bit and one 16/24-bit Output
• High-Performance Sitara™ ARM® Processors
• ARM® Cortex™-A8 Core
•
– Composite or S-Video Analog Output
– MacroVision® Support Available
– Digital HDMI 1.3 transmitter With Integrated
PHY
– Advanced Video Processing Features Such
as Scan/Format/Rate Conversion
– ARMv7 Architecture
•
In-Order, Dual-Issue, Superscalar
Processor Core
•
•
•
NEON™ Multimedia Architecture
Supports Integer and Floating Point
Jazelle® RCT Execution Environment
– Three Graphics Layers and Compositors
• Dual 32-bit DDR2/DDR3 SDRAM Interfaces
– Supports up to DDR2-800 and DDR3-800
• ARM® Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 512K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• 128K-Bytes On-Chip Memory Controller
(OCMC) RAM
– Up to Eight x 8 Devices Total 2 GB Total
Address Space
– Dynamic Memory Manager (DMM)
•
Programmable Multi-Zone Memory
Mapping and Interleaving
• Imaging Subsystem (ISS)
– Camera Sensor Connection
•
•
Enables Efficient 2D Block Accesses
Supports Tiled Objects in 0°, 90°, 180°, or
270° Orientation and Mirroring
•
Parallel Connection for Raw (up to 16-Bit)
and BT.656/BT.1120 (8-/16-bit)
– Image Sensor Interface (ISIF) for Handling
Image/Video Data From the Camera Sensor
– Resizer
•
Optimizes Interlaced Accesses
• General Purpose Memory Controller (GPMC)
– 8-/16-bit Multiplexed Address/Data Bus
•
•
Resizing Image/Video From 1/16x to 8x
Generating Two Different Resizing
Outputs Concurrently
– 512M-Byte Total Address Space Divided
Among up to 8 Chip Selects
– Glueless Interface to NOR Flash, NAND
Flash (BCH/Hamming Error Code Detection),
SRAM and Pseudo-SRAM
– Error Locator Module (ELM) Outside of
GPMC to Provide Upto 16-Bit/512-Bytes
Hardware ECC for NAND
• Media Controller
– Controls the HDVPSS and ISS
• SGX530 3D Graphics Engine
– Delivers up to 25 MPoly/sec
– Universal Scalable Shader Engine
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
OpenVG 1.0, OpenMax API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– Flexible Asynchronous Protocol Control for
Interface to FPGA, CPLD, ASICs, and so
Forth
• Enhanced Direct-Memory-Access (EDMA)
Controller
– Four Transfer Controllers
– 64/8 Independent DMA/QDMA Channels
• Dual Port Ethernet (10/100/1000 Mb/s) With
Optional Switch
– ARM Instructions/Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
– Two 165 MHz HD Video Capture Inputs
•
One 16/24-bit Input, Splittable into Dual 8-
bit SD Capture Ports
– IEEE 802.3 Compliant (3.3V I/O Only)
– MII/RMII/GMII/RGMII Media Independent I/Fs
– Management Data I/O (MDIO) Module
•
•
One 8/16/24-bit Input
One 8-bit Only Input
1
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2
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