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AM27C64-120DC PDF预览

AM27C64-120DC

更新时间: 2024-11-14 20:20:43
品牌 Logo 应用领域
飞索 - SPANSION 可编程只读存储器
页数 文件大小 规格书
12页 172K
描述
UVPROM, 8KX8, 120ns, CMOS, CDIP28, CERAMIC, DIP-28

AM27C64-120DC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP28,.6针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.61风险等级:5.65
最长访问时间:120 nsI/O 类型:COMMON
JESD-30 代码:R-CDIP-T28JESD-609代码:e0
长度:37.147 mm内存密度:65536 bit
内存集成电路类型:UVPROM内存宽度:8
湿度敏感等级:1功能数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装等效代码:DIP28,.6封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:5 V
编程电压:12.75 V认证状态:Not Qualified
座面最大高度:5.588 mm最大待机电流:0.0001 A
子类别:EPROMs最大压摆率:0.025 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:15.24 mm
Base Number Matches:1

AM27C64-120DC 数据手册

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FINAL  
Am27C64  
64 Kilobit (8 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
— Speed options as fast as 45 ns  
Low power consumption  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
— 20 µA typical CMOS standby current  
JEDEC-approved pinout  
Single +5 V power supply  
Standard 28-pin DIP, PDIP, and 32-pin PLCC  
±10% power supply tolerance standard  
100% Flashrite™ programming  
Typical programming time of 1 second  
packages  
GENERAL DESCRIPTION  
The Am27C64 is a 64-Kbit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 8K  
words by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 80 mW in active mode, and  
100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 1 second.  
Data can be typically accessed in less than 45 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
OE#  
CE#  
Output Enable  
Chip Enable  
and  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A12  
Address  
Inputs  
65,538  
Bit Cell  
Matrix  
X
Decoder  
11419E-1  
Publication# 11419 Rev: E Amendment/0  
Issue Date: May 1998  

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