Datasheet > AM27C512-55JC5

AM27C512-55JC5

更新时间： 2024-01-19 14:23:22

品牌	Logo	应用领域
飞索 - SPANSION		OTP只读存储器内存集成电路
页数	文件大小	规格书
12页	175K
描述
OTP ROM, 64KX8, 55ns, CMOS, PQCC32, PLASTIC, LCC-32

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AM27C512-55JC5 技术参数

生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	QCCJ,	针数：	32
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.54
Is Samacsys：	N	最长访问时间：	55 ns
JESD-30 代码：	R-PQCC-J32	长度：	13.97 mm
内存密度：	524288 bit	内存集成电路类型：	OTP ROM
内存宽度：	8	功能数量：	1
端子数量：	32	字数：	65536 words
字数代码：	64000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	3.556 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	11.43 mm
Base Number Matches：	1

AM27C512-55JC5 数据手册

FINAL

Am27C512

512 Kilobit (64 K x 8-Bit) CMOS EPROM

DISTINCTIVE CHARACTERISTICS

n Fast access time

n Latch-up protected to 100 mA from –1 V to

V_CC+ 1 V

— Speed options as fast as 55 ns

n Low power consumption

n High noise immunity

n Versatile features for simple interfacing

— Both CMOS and TTL input/output compatibility

— Two line control functions

— 20 µA typical CMOS standby current

n JEDEC-approved pinout

n Single +5 V power supply

n Standard 28-pin DIP, PDIP, and 32-pin PLCC

n ±10% power supply tolerance standard

n 100% Flashrite™ programming

— Typical programming time of 8 seconds

packages

GENERAL DESCRIPTION

The Am27C512 is a 512-Kbit, ultraviolet erasable pro-

grammable read-only memory. It is organized as 64K

words by 8 bits per word, operates from a single +5 V

supply, has a static standby mode, and features fast

single address location programming. Products are

available in windowed ceramic DIP packages, as well

as plastic one time programmable (OTP) PDIP and

PLCC packages.

thus eliminating bus contention in a multiple bus micro-

processor system.

AMD’s CMOS process technology provides high

speed, low power, and high noise immunity. Typical

power consumption is only 80 mW in active mode, and

100 µW in standby mode.

All signals are TTL levels, including programming sig-

nals. Bit locations may be programmed singly, in

blocks, or at random. The device supports AMD’s

Flashrite programming algorithm (100 µs pulses), re-

sulting in a typical programming time of 8 seconds.

Data can be typically accessed in less than 55 ns, al-

lowing high-performance microprocessors to operate

without any WAIT states. The device offers separate

Output Enable (OE#) and Chip Enable (CE#) controls,

BLOCK DIAGRAM

Data Outputs

DQ0–DQ7

Output Enable

Chip Enable

and

OE#/V

Output

Buffers

CE#

Prog Logic

Gating

Decoder

A0–A15

Address

Inputs

524,288

Bit Cell

Matrix

Decoder

08140J-1

Publication# 08140 Rev: J Amendment/+2

Issue Date: June 1, 1999

12 3 4 5 6 7...12

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与AM27C512-55JC5相关器件

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AM27C512-55PC	ROCHESTER	512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns	获取价格
AM27C512-55PC5	ROCHESTER	512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns	获取价格
AM27C512-70DC	SPANSION	UVPROM, 64KX8, 70ns, CMOS, CDIP28, CERAMIC, DIP-28	获取价格
AM27C512-70DC	AMD	512 Kilobit (64 K x 8-Bit) CMOS EPROM	获取价格
AM27C512-70DC	ROCHESTER	512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns	获取价格
AM27C512-70DCB	ROCHESTER	512 Kilobit ( 64 K x 8-Bit ) CMOS EPROM Speed options as fast as 55 ns	获取价格

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