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AM27C1024-200DE5B PDF预览

AM27C1024-200DE5B

更新时间: 2024-11-27 22:30:23
品牌 Logo 应用领域
超微 - AMD 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
12页 166K
描述
1 Megabit (65 K x 16-Bit) CMOS EPROM

AM27C1024-200DE5B 数据手册

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FINAL  
Am27C1024  
1 Megabit (65 K x 16-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
±10% power supply tolerance standard  
100% Flashrite™ programming  
— Speed options as fast as 55 ns  
Low power consumption  
— 20 µA typical CMOS standby current  
JEDEC-approved pinout  
— 40-Pin DIP/PDIP  
Typical programming time of 8 seconds  
Latch-up protected to 100 mA from –1 V to  
VCC + 1 V  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
— 44-Pin PLCC  
Single +5 V power supply  
GENERAL DESCRIPTION  
The Am27C1024 is a 1 Megabit, ultraviolet erasable  
programmable read-only memory. It is organized as 64  
Kwords by 16 bits per word, operates from a single  
+5 V supply, has a static standby mode, and features  
fast single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 125 mW in active mode,  
and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 8 seconds.  
Data can be typically accessed in less than 55 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ15  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
CE#  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A15  
Address  
Inputs  
1,048,576  
Bit Cell  
Matrix  
X
Decoder  
06780J-1  
Publication# 06780 Rev: J Amendment/0  
Issue Date: May 1998  

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