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AM27C010-120JI PDF预览

AM27C010-120JI

更新时间: 2024-01-24 06:49:57
品牌 Logo 应用领域
飞索 - SPANSION OTP只读存储器
页数 文件大小 规格书
12页 178K
描述
OTP ROM, 128KX8, 120ns, CMOS, PQCC32, PLASTIC, LCC-32

AM27C010-120JI 技术参数

生命周期:Obsolete零件包装代码:QFJ
包装说明:QCCJ,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.33
Is Samacsys:N最长访问时间:120 ns
JESD-30 代码:R-PQCC-J32长度:13.97 mm
内存密度:1048576 bit内存集成电路类型:OTP ROM
内存宽度:8功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:3.556 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:11.43 mm
Base Number Matches:1

AM27C010-120JI 数据手册

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FINAL  
Am27C010  
1 Megabit (128 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
100% Flashrite™ programming  
— Speed options as fast as 45 ns  
Low power consumption  
Typical programming time of 16 seconds  
Latch-up protected to 100 mA from –1 V to  
V
+ 1 V  
CC  
— 20 µA typical CMOS standby current  
JEDEC-approved pinout  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
Single +5 V power supply  
±10% power supply tolerance standard  
Standard 32-pin DIP, PDIP, and PLCC packages  
GENERAL DESCRIPTION  
The Am27C010 is a 1 Megabit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 128K  
words by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 100 mW in active mode,  
and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 16 seconds.  
Data can be typically accessed in less than 45 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
CE#  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A16  
Address  
Inputs  
1,048,576  
Bit Cell  
Matrix  
X
Decoder  
10205J-1  
Publication# 10205 Rev: J Amendment/0  
Issue Date: July 2, 1999  

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