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AM27C010-120DI PDF预览

AM27C010-120DI

更新时间: 2024-01-01 18:28:01
品牌 Logo 应用领域
飞索 - SPANSION 可编程只读存储器电动程控只读存储器内存集成电路
页数 文件大小 规格书
12页 178K
描述
UVPROM, 128KX8, 120ns, CMOS, CDIP32, CERAMIC, DIP-32

AM27C010-120DI 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.61风险等级:5.07
最长访问时间:120 nsJESD-30 代码:R-CDIP-T32
长度:42.1 mm内存密度:1048576 bit
内存集成电路类型:UVPROM内存宽度:8
功能数量:1端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:5.588 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:15.24 mmBase Number Matches:1

AM27C010-120DI 数据手册

 浏览型号AM27C010-120DI的Datasheet PDF文件第2页浏览型号AM27C010-120DI的Datasheet PDF文件第3页浏览型号AM27C010-120DI的Datasheet PDF文件第4页浏览型号AM27C010-120DI的Datasheet PDF文件第5页浏览型号AM27C010-120DI的Datasheet PDF文件第6页浏览型号AM27C010-120DI的Datasheet PDF文件第7页 
FINAL  
Am27C010  
1 Megabit (128 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
100% Flashrite™ programming  
— Speed options as fast as 45 ns  
Low power consumption  
Typical programming time of 16 seconds  
Latch-up protected to 100 mA from –1 V to  
V
+ 1 V  
CC  
— 20 µA typical CMOS standby current  
JEDEC-approved pinout  
High noise immunity  
Versatile features for simple interfacing  
— Both CMOS and TTL input/output compatibility  
Two line control functions  
Single +5 V power supply  
±10% power supply tolerance standard  
Standard 32-pin DIP, PDIP, and PLCC packages  
GENERAL DESCRIPTION  
The Am27C010 is a 1 Megabit, ultraviolet erasable pro-  
grammable read-only memory. It is organized as 128K  
words by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one time programmable (OTP) PDIP and  
PLCC packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 100 mW in active mode,  
and 100 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses), re-  
sulting in a typical programming time of 16 seconds.  
Data can be typically accessed in less than 45 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
CE#  
Output  
Buffers  
Prog Logic  
PGM#  
Y
Y
Gating  
Decoder  
A0–A16  
Address  
Inputs  
1,048,576  
Bit Cell  
Matrix  
X
Decoder  
10205J-1  
Publication# 10205 Rev: J Amendment/0  
Issue Date: July 2, 1999  

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