Order this document by AM26LS32/D
QUAD EIA–422/3 LINE
RECEIVER WITH
THREE–STATE OUTPUTS
Motorola′s Quad EIA–422/3 Receiver features four independent receiver
chains which comply with EIA Standards for the Electrical Characteristics of
Balanced/Unbalanced Voltage Digital Interface Circuits. Receiver outputs
are 74LS compatible, three–state structures which are forced to a high
impedance state when Pin 4 is a Logic “0” and Pin 12 is a Logic “1.” A PNP
device buffers each output control pin to assure minimum loading for either
Logic “1” or Logic “0” inputs. In addition, each receiver chain has internal
hysteresis circuitry to improve noise margin and discourage output instability
for slowly changing input waveforms. A summary of AM26LS32 features
include:
SEMICONDUCTOR
TECHNICAL DATA
D SUFFIX
PLASTIC PACKAGE
CASE 751B
• Four Independent Receiver Chains
• Three–State Outputs
(SO–16)
• High Impedance Output Control Inputs
(PIA Compatible)
• Internal Hysteresis – 30 mV (Typical) @ Zero Volts Common Mode
• Fast Propagation Times – 25 ns (Typical)
• TTL Compatible
PC SUFFIX
PLASTIC PACKAGE
CASE 648
• Single 5.0 V Supply Voltage
• Fail–Safe Input–Output Relationship. Output Always High When Inputs
Are Open, Terminated or Shorted
• 6.0 k Minimum Input Impedance
PIN CONNECTIONS
V
1
2
3
4
5
6
7
8
16
15
14
–
+
CC
Representative Block Diagram
Inputs A
–
+
Inputs B
Three–State
Outputs A
Differential
Inputs
Control
Inputs
3–State
Control
Output
13 Output B
3–State
12
Output C
Control
Output D
Inputs D
11
10
9
+
–
Inputs C
Input
Network
+
–
GND
Level
Translator
Amplifier
Hysteresis
ORDERING INFORMATION
Operating
Level
Translator
Amplifier
Temperature Range
Device
Package
AM26LS32PC
MC26LS32D*
Plastic DIP
SO–16
T
A
= 0 to 70°C
* Note that the surface mount MC26LS32D device uses the same die as in the plastic DIP
* AM26LS32DC device, but with an MC prefix to prevent confusion with the package suffix.
Motorola, Inc. 1995
1
MOTOROLA ANALOG IC DEVICE DATA