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ALVTH16245

更新时间： 2024-11-26 03:18:39
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德州仪器 - TI 总线收发器输出元件
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24页 683K
描述
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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ALVTH16245 数据手册

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SN54ALVTH16245, SN74ALVTH16245  
2.5-V/3.3-V 16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCES066G – JUNE 1996 – REVISED APRIL 2002  
SN54ALVTH16245 . . . WD PACKAGE  
SN74ALVTH16245 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Widebus Design for  
2.5-V and 3.3-V Operation and Low  
Static-Power Dissipation  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
2
3
3.6-V V  
)
CC  
4
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
5
OLP  
CC  
= 3.3 V, T = 25°C  
6
A
7
V
V
High Drive (–32/64 mA at 3.3-V V  
)
CC  
CC  
CC  
8
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
I
and Power-Up 3-State Support Hot  
off  
9
Insertion  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Use Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
V
CC  
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
description  
The ’ALVTH16245 devices are 16-bit (dual-octal)  
noninverting 3-state transceivers designed for  
2DIR  
2.5-V or 3.3-V V  
operation, but with the  
CC  
capability to provide a TTL interface to a 5-V  
system environment.  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. They allow data transmission  
from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control  
(DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively  
isolated.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup  
or pulldown resistors with the bus-hold circuitry is not recommended.  
When V is between 0 and 1.2 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...24

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