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ASM2I20805AG-20-DT PDF预览

ASM2I20805AG-20-DT

更新时间: 2024-01-17 21:16:57
品牌 Logo 应用领域
ALSC 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 485K
描述
2.5V CMOS Dual 1-To-5 Clock Driver

ASM2I20805AG-20-DT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:GREEN, QSOP-20Reach Compliance Code:unknown
风险等级:5.68Is Samacsys:N
系列:20805输入调节:STANDARD
JESD-30 代码:R-PDSO-G20JESD-609代码:e3/e6
长度:8.65 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
功能数量:2反相输出次数:
端子数量:20实输出次数:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
传播延迟(tpd):3 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.27 ns座面最大高度:1.73 mm
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN/TIN BISMUTH端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

ASM2I20805AG-20-DT 数据手册

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June 2005  
rev 0.2  
ASM2P20805A  
2.5V CMOS Dual 1-To-5 Clock Driver  
Functional Description  
Features  
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Advanced CMOS Technology  
The ASM2P20805A is a 2.5V Clock driver built using  
advanced CMOS technology. The device consists of two  
banks of drivers, each with a 1:5 fanout and its own output  
enable control. The device has a "heartbeat" monitor for  
diagnostics and PLL driving. The MON output is identical to  
all other outputs and complies with the output specifications  
in this document. The ASM2P20805A offers low  
capacitance inputs. The ASM2P20805A is designed for  
high speed clock distribution where signal quality and skew  
are critical. The ASM2P20805A also allows single point-to-  
point transmission line driving in applications such as  
address distribution, where one signal must be distributed  
to multiple receivers with low skew and high signal quality.  
Guaranteed low skew < 200pS (max.)  
Very low propagation delay < 2.5nS (max)  
Very low duty cycle distortion < 270pS (max)  
Very low CMOS power levels  
Operating frequency up to 166MHz  
TTL compatible inputs and outputs  
Two independent output banks with 3-state control  
1:5 fanout per bank  
"Heartbeat" monitor output  
VCC = 2.5V ± 0.2V  
Available in SSOP and QSOP packages  
Block Diagram  
Pin Diagram  
VCCA  
OEA  
INA  
VCCB  
OB1  
1
2
20  
19  
OA1  
OA2  
5
OA1 – OA5  
A
S
M
2
OB2  
OB3  
GNDB  
OB4  
OB5  
MON  
OEB  
INB  
3
4
18  
17  
16  
15  
OA3  
GNDA  
OA4  
5
P
2
5
INB  
OB1 – OB5  
MON  
6
7
0
8
OA5  
14  
OEB  
0
GNDQ  
OEA  
8
13  
12  
11  
5
A
9
INA  
10  
Alliance Semiconductor  
2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com  
Notice: The information in this document is subject to change without notice.  

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