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AS4LC1M16S0-7TC PDF预览

AS4LC1M16S0-7TC

更新时间: 2024-02-24 06:49:57
品牌 Logo 应用领域
ALSC 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
29页 720K
描述
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM

AS4LC1M16S0-7TC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:50Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.7Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:5.5 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PDSO-G50
长度:20.95 mm内存密度:16777216 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:50字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE认证状态:Not Qualified
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

AS4LC1M16S0-7TC 数据手册

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AS4LC2M8S1  
AS4LC2M8S0  
AS4LC1M16S1  
AS4LC1M16S0  
May 2001  
Preliminary  
®
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM  
Features  
• Organization  
- 1,048,576 words × 8 bits × 2 banks (2M × 8)  
11 row, 9 column address  
- 524,288 words × 16 bits × 2 banks (1M × 16)  
11 row, 8 column address  
• All signals referenced to positive edge of clock, fully  
synchronous  
• Dual internal banks controlled by A11 (bank select)  
• High speed  
- 143/125/100 MHz  
- 7/8/10 ns clock access time  
• Low power consumption  
- Active: 576 mW max  
- Standby: 7.2 mW max, CMOS I/O  
• 2048 refresh cycles, 32 ms refresh interval  
• 4096 refresh cycles, 64 ms refresh interval  
• Auto refresh and self refresh  
• PC100 functionality  
• Automatic and direct precharge including concurrent  
autoprecharge  
• Burst read, write/Single write  
• Random column address assertion in every cycle, pipelined  
operation  
• LVTTL compatible I/O  
• 3.3V power supply  
• JEDEC standard package, pinout and function  
- 400 mil, 44-pin TSOP 2 (2M × 8)  
- 400 mil, 50-pin TSOP 2 (1M × 16)  
• Read/write data masking  
• Programmable burst length (1/2/4/8/ full page)  
• Programmable burst sequence (sequential/interleaved)  
• Programmable CAS latency (1/2/3)  
Pin arrangement  
Pin designation  
TSOP 2  
50  
TSOP 2  
Pin(s)  
Description  
V
V
SS  
V
V
SS  
1
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
CC  
1
CC  
DQ0  
DQ1  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
DQ15  
DQ14  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
DQ0  
DQ7  
2
DQM (2M × 8)  
UDQM/LDQM (1M × 16)  
V
V
3
SSQ  
SSQ  
Output disable/write mask  
V
V
SSQ  
SSQ  
DQ6  
4
DQ1  
DQ13  
V
V
DQ2  
DQ3  
5
CCQ  
CCQ  
DQ12  
RA0 – 10  
Address inputs CA0 – 7 (×16)  
CA0 – 8 (×8)  
DQ2  
DQ5  
6
V
V
V
V
CCQ  
DQ4  
DQ5  
CCQ  
7
SSQ  
SSQ  
A0 to A10  
A11  
DQ11  
DQ10  
DQ3  
DQ4  
8
V
V
CCQ  
NC  
9
CCQ  
V
V
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
SSQ  
SSQ  
DQ6  
DQ7  
DQ9  
DQ8  
NC  
WE  
CAS  
NC  
DQM  
CLK  
Bank address (BA)  
V
V
CCQ  
CCQ  
DQ0 to DQ7 (2M × 8)  
DQ0 to DQ15 (1M × 16)  
LDQM  
Input/output  
NC  
UDQM  
CLK  
CKE  
NC  
A9  
A8  
A7  
A6  
A5  
RAS  
CS  
A11  
A10  
A0  
A1  
A2  
A3  
CKE  
NC  
A9  
A8  
A7  
A6  
A5  
A4  
WE  
CAS  
RAS  
CS  
A11  
A10  
A0  
A1  
A2  
A3  
RAS  
CAS  
Row address strobe  
Column address strobe  
Write enable  
WE  
V
V
CC  
SS  
CS  
Chip select  
23  
24  
25  
28  
27  
26  
A4  
VCC, VCCQ  
VSS, VSSQ  
CLK  
Power (3.3V 0.3V)  
Ground  
V
V
CC  
SS  
LEGEND  
2M × 8  
1M × 16  
512K × 16 × 2 banks  
2K/4K  
Configuration  
Refresh Count  
Row Address  
Bank Address  
Column Address  
1M × 8 × 2 banks  
2K/4K  
Clock input  
(A0 – A10)  
2 (BA)  
512 (A0 – A8)  
(A0 – A10)  
2 (BA)  
256 (A0 – A7)  
CKE  
Clock enable  
Selection guide  
Symbol  
fMax  
tAC  
–7  
143  
5.5  
2
–8  
125  
6
–10  
100  
6
Unit  
MHz  
ns  
Bus frequency (CL = 3)  
Maximum clock access time (CL = 3)  
Minimum input setup time  
Minimum input hold time  
tS  
2
2
ns  
tH  
1.0  
70  
1.0  
80  
1.0  
80  
ns  
Row cycle time (CL = 3, BL = 1)  
tRC  
ns  
Maximum operating current ([×16], RD or  
ICC1  
130  
1
100  
1
100  
mA  
mA  
WR, CL = 3), BL = 2  
Maximum CMOS standby current, self refresh  
ICC6  
1
5/21/01; v.1.1  
Alliance Semiconductor  
P. 1 of 29  
Copyright ©Alliance Semiconductor. All rights reserved.  

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