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A6800SL-T PDF预览

A6800SL-T

更新时间: 2024-02-05 09:04:52
品牌 Logo 应用领域
急速微 - ALLEGRO 外围驱动器驱动程序和接口接口集成电路光电二极管信息通信管理
页数 文件大小 规格书
12页 435K
描述
DABiC-5 Latched Sink Drivers

A6800SL-T 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:LEAD FREE, MS-012AB, SOIC-14
针数:14Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.83内置保护:TRANSIENT
驱动器位数:1接口集成电路类型:LATCH BASED PERIPHERAL DRIVER
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:9.9 mm湿度敏感等级:2
功能数量:1端子数量:14
最高工作温度:85 °C最低工作温度:-20 °C
输出电流流向:SINK封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3/5 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Peripheral Drivers
最大供电电压:5.5 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:BIMOS温度等级:OTHER
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

A6800SL-T 数据手册

 浏览型号A6800SL-T的Datasheet PDF文件第2页浏览型号A6800SL-T的Datasheet PDF文件第3页浏览型号A6800SL-T的Datasheet PDF文件第4页浏览型号A6800SL-T的Datasheet PDF文件第5页浏览型号A6800SL-T的Datasheet PDF文件第6页浏览型号A6800SL-T的Datasheet PDF文件第7页 
A6800/A6801  
DABiC-5 Latched Sink Drivers  
The A6800 and A6801 latched-input BiMOS ICs merge high-current,  
high-voltage outputs with CMOS logic. The CMOS input section con-  
sists of 4 or 8 data (‘D’ type) latches with associated common CLEAR,  
STROBE, and OUTPUT ENABLE circuitry. The power outputs are  
bipolar NPN Darlingtons. This merged technology provides versatile,  
exible interface. These BiMOS power interface ICs greatly benet the  
simplication of computer or microprocessor I/O. The A6800 ICs each  
contain four latched drivers. A6801 ICs contain eight latched drivers.  
A6800SA  
A6800SL  
The CMOS inputs are compatible with standard CMOS circuits. TTL  
circuits may mandate the addition of input pull-up resistors. The bipolar  
Darlington outputs are suitable for directly driving many peripheral/  
power loads: relays, lamps, solenoids, small dc motors, etc.  
All devices have open-collector outputs and integral diodes for induc-  
tive load transient suppression. The output transistors are capable of  
sinking 600 mA and will withstand at least 50 V in the OFF state.  
Because of limitations on package power dissipation, the simultaneous  
operation of all drivers at maximum rated current can only be accom-  
plished by a reduction in duty cycle. Outputs may be paralleled for  
higher load current capability.  
A6801SA  
A6801SEP  
The A6800SA is furnished in a standard 14-pin DIP; the A6800SL and  
A6801SLW in surface-mountable SOICs; the A6801SA in a 22-pin  
DIP with 0.400” (10.16 mm) row centers; the A6801SEP in a 28-lead  
PLCC. These devices are lead (Pb) free, with 100% matte tin plated  
leadframes.  
A6801SLW  
ABSOLUTE MAXIMUM RATINGS  
FEATURES  
„
„
„
„
3.3 V to 5Vlogic supply range  
„
„
„
„
CMOS, TTL compatible inputs  
Output transient protection  
Internal pull-down resistors  
Low-power CMOS latches  
Output Voltage, VCE............................................50 V  
Supply Voltage, VDD.............................................7 V  
Input Voltage Range,VIN ..............–0.3VtoVDD +0.3V  
Continuous Collector Current, IC........................ 600 mA  
Package Power Dissipation, PD, see Allowable Power  
Disspation chart, page 5  
To 10 MHz data input rate  
High-voltage, high-current outputs  
Darlington current-sink outputs, with  
improved low-saturation voltages  
APPLICATIONS  
Operating Temperature Range  
„
„
Solenoids  
Small dc motors  
„
„
Relays  
Lamps  
Ambient Temperature, TA............–20°C to +85°C  
Storage Temperature, TS ..........–55°C to +150°C  
Use the following complete part numbers when ordering:  
Part Number  
A6800SA-T  
A6800SL-T  
A6801SA-T  
A6801SEP-T  
A6801SLW-T  
Pins  
14  
Package  
DIP  
Caution: CMOS devices have input-static protection,  
but are susceptible to damage when exposed to  
extremely high static-electrical charges.  
14  
SOIC  
DIP  
22  
28  
PLCC  
SOIC  
24  

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