A
L
D
DVANCED
INEAR
EVICES, INC.
ALD1103
DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR
GENERAL DESCRIPTION
APPLICATIONS
The ALD1103 is a monolithic dual N-channel and dual P-channel matched
transistor pair intended for a broad range of analog applications. These
enhancement-mode transistors are manufactured with Advanced Linear
Devices' enhanced ACMOS silicon gate CMOS process. It consists of an
ALD1101 N-channel MOSFET pair and an ALD1102 P-channel MOSFET
pair in one package.
• Precision current mirrors
• Complementary push-pull linear drives
• Analog switches
• Choppers
• Differential amplifier input stage
• Voltage comparator
• Data converters
• Sample and Hold
• Analog inverter
• Precision matched current sources
TheALD1103offershighinputimpedanceandnegativecurrenttemperature
coefficient. The transistor pair is matched for minimum offset voltage and
differential thermal response, and it is designed for precision signal
switching and amplifying applications in +2V to +12V systems where low
input bias current, low input capacitance and fast switching speed are
desired. SincetheseareMOSFETdevices, theyfeatureverylarge(almost
infinite)currentgaininalowfrequency,ornearDC,operatingenvironment.
When used in pairs, a dual CMOS analog switch can be constructed. In
addition, the ALD1103 is intended as a building block for differential
amplifier input stages, transmission gates, and multiplexer applications.
PIN CONFIGURATION
DN1
GN1
SN1
1
2
3
4
5
6
14
13
DN2
GN2
12 SN2
+
The ALD1103 is suitable for use in precision applications which require
very high current gain, beta, such as current mirrors and current sources.
The high input impedance and the high DC current gain of the Field Effect
Transistors result in extremely low current loss through the control gate.
The DC current gain is limited by the gate input leakage current, which is
specifiedat50pAatroomtemperature. Forexample, DCbetaofthedevice
at a drain current of 5mA at 25°C is = 5mA/50pA = 100,000,000.
-
V
11
10
9
V
DP1
GP1
SP1
DP2
GP2
8
SP2
7
FEATURES
DB, PB, SB PACKAGE
• Thermal tracking between N-channel and P-channel pairs
• Low threshold voltage of 0.7V for both N-channel &
P-channel MOSFETS
BLOCK DIAGRAM
• Low input capacitance
N GATE 1 (2)
• Low Vos -- 10mV
• High input impedance -- 1013Ω typical
• Low input and output leakage currents
N SOURCE 1 (3)
SUBSTRATE (4)
N DRAIN 1 (1)
N DRAIN 2 (14)
• Negative current (I ) temperature coefficient
DS
• Enhancement mode (normally off)
• DC current gain 109
N SOURCE 2 (12)
• Matched N-channel and matched P-channel in one package
N GATE 2 (13)
P GATE 1 (6)
ORDERING INFORMATION
Operating Temperature Range*
-55°C to +125°C
0°C to +70°C
0°C to +70°C
P SOURCE 1 (7)
SUBSTRATE (11)
P DRAIN 1 (5)
P DRAIN 2 (10)
14-Pin
CERDIP
Package
14-Pin
Plastic Dip
Package
14-Pin
SOIC
Package
P SOURCE 2 (8)
ALD1103 DB
ALD1103 PB
ALD1103 SB
P GATE 2 (9)
* Contact factory for industrial temperature range.
© 1998 Advanced Linear Devices, Inc. 415Tasman Drive, Sunnyvale, California 94089 -1706 Tel: (408) 747-1155 Fax: (408) 747-1286 http://www.aldinc.com