Datasheet > AL5DS9269V

AL5DS9269V

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
凌泰科技 - AVERLOGIC		静态存储器
页数	文件大小	规格书
2页	117K
描述
3.3V Synchronous Dual-Port SRAM 4K/8K/16K/32K/64K/128K x 8/9/16/18-bit

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数据手册

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AL5DS9269V 数据手册

AL5DS9xx9V

3.3V Synchronous Dual-Port SRAM

4K/8K/16K/32K/64K/128K x 8/9/16/18-bit

Features

ò True dual ported memory cells

ò 17 Flow-Through/Pipelined devices:

-- 4K/8K/16K/32K/64K x 18-bit organization (AL5DS9349V/59V/69V/79V/89V)

-- 16K/32K/64K x 16-bit organization (AL5DS9269V/79V/89V)

-- 8K/16K/32K/64K/128K x 9-bit organization (AL5DS9159V/69V/79V/89V/99V)

-- 16K/32K/64K/128K x 8-bit organization (AL5DS9069V/79V/89V/99V)

ò Supports byte write/read for 16/18 bit devices

ò Separate upper-byte and lower-byte controls for bus matching (16/18 bit devices only)

ò 3 modes supported:

-Pipelined

-Flow-Through

-Burst

ò Counter enable and reset

ò Fast (100-MHz) operation on both ports in Pipelined output mode

ò Supports depth and width expansion

ò 0.25-micron CMOS for optimum speed / power

ò High speed clock to data access

ò 3.3V low operating power

ò Pin-compatible and functionally equivalent to IDT or Cypress

Available in 100 or 128 pin TQFP

Architecture

ˣ˜ˣ˘˂˙˧_˥

ˣ˜ˣ˘˂˙˧_˟

˖˘_˄˟

˖˘_˃˟

˖˘_˄˥

˖˘_˃˥

˥˂˪_˟

˟˕_˟

˨˕_˟

˥˂˪_˥

˟˕_˥

˨˕_˥

˟˸˹̇ʳ˜˂ˢ

˖̂́̇̅̂˿

˥˼˺˻̇ʳ˜˂ˢ

˖̂́̇̅̂˿

ˢ˘_˟

ˢ˘_˥

ˋ˂ˌ

˜˂ˢ_{ˋ˂ˌ˟̑˄ˈ˂˄ˊ˟}

˜˂ˢ_{˃˟̑ˊ˂ˋ˟}

˜˂ˢ_{ˋ˂ˌ˥̑˄ˈ˂˄ˊ˥}

˜˂ˢ_{˃˥̑ˊ˂ˋ˥}

˖˟˞_˟

˖˟˞_˥

˄˅̑˄ˊ

˃˥̑˄ˉ˥

˃˟̑˄ˉ˟

˟˸˹̇

˔˷˷̅˸̆̆

˖̂́̇̅̂˿

˥˼˺˻̇

˔˷˷̅˸̆̆

˖̂́̇̅̂˿

˔˗˦_˟

˔˗˦_˥

˖ˡ˧˘ˡ_˥

˖ˡ˧˥˦˧_˥

˧̅̈˸ʳ˗̈˴˿ˀˣ̂̅̇˸˷ʳ˦˥˔ˠ

˖ˡ˧˘ˡ_˟

˖ˡ˧˥˦˧_˟

ˡ̂̇˸ʳ˄ˍʳ˟˕_˥ʳ˴́˷ʳ˨˕_˥ʳ˴̅˸ʳ˹̂̅ʳʳ˄ˉ˂˄ˋʳ˵˼̇ʳ˷˸̉˼˶˸̆ʳ̂́˿̌ˁ

ˡ̂̇˸ʳ˅ˍʳ˜˂ˢ_˃̑ˊʳ˹̂̅ʳʳˋ˂˄ˉʳ˵˼̇ʳ˷˸̉˼˶˸̆ʿʳ˜˂ˢ_˃̑ˋʳ˹̂̅ʳʳˌ˂˄ˋʳ˵˼̇ʳ˷˸̉˼˶˸̆ʿʳ˜˂ˢ_ˋ̑˄ˈʳ˹̂̅ʳ˄ˉʳ˵˼̇ʳ˷˸̉˼˶˸̆ʿʳ˴́˷ʳ˜˂ˢ_ˌ̑˄ˊʳ˹̂̅ʳʳ˄ˋʳ˵˼̇ʳ˷˸̉˼˶˸̆ˁ

ˡ̂̇˸ʳˆˍʳ˔_˃̑˄˄ʳ˹̂̅ʳˇ˞ʿʳ˔_˃̑˄˅ʳ˹̂̅ʳˋ˞ʿʳ˔_˃̑˄ˆʳ˹̂̅ʳ˄ˉ˞ʿʳ˔_˃̑˄ˇʳ˹̂̅ʳˆ˅˞ʿʳ˔_˃̑˄ˈʳ˹̂̅ʳˉˇ˞ʿʳ˴́˷ʳ˔_˃̑˄ˉʳ˹̂̅ʳ˄˅ˋ˞ʳ˷˸̉˼˶˸̆

AL5DS9xx9V Preliminary Rev: 1.0

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