Datasheet > AL5DA132

AL5DA132

更新时间： 2024-11-09 03:18:35

品牌	Logo	应用领域
凌泰科技 - AVERLOGIC		静态存储器
页数	文件大小	规格书
2页	80K
描述
3.3V, 5V Asynchronous Dual-Port SRAM 1k/2k/4K/8K/16K/32K x 8/9/16/18-bit

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中文翻译

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数据手册

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AL5DA132 数据手册

AL5DAxxxx

3.3V, 5V Asynchronous Dual-Port SRAM

1k/2k/4K/8K/16K/32K x 8/9/16/18-bit

Features

! True dual port memory cells up to 256/288Kb

! Fully asynchronous dual-port SRAM aimed at communications market

! Max. access time: 30 ns

! Separate upper byte and lower byte control for multiplexed bus compatibility (only for 16/18 bit

devices)

! Supports byte write/read for 16/18 bit devices

! On-chip arbitration logic support 3 modes: Busy, Interrupt and Semaphore

Busy scheme circuit arbitrate between 2 ports

interrupt mechanism allow port to port communication

Full hardware support of semaphore to permit software handshaking between ports

! Versatile pin select for Master or Slave mode:

M/S = V_IH

M/S = V_IL

for

output flag on master;

input flag on slave

BUSY

! Expandable data bus to 32/36 bits or more using master/slave chip select when using more than one

device

! Separate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)

! 3.3v and 5v series low power respectively

! Compatible and functionally equivalent to IDT or Cypress

! Available in 52-PLCC, 68-PLCC, 84-PLCC, 64-TQFP/STQFP, 80-TQFP, 100-TQFP

Architecture

IO _8/9L-15/17R

IO_8/9L-15/17L

0L -7/8L

0R -7/8R

10L -14L

10R -14R

0L - 9L

0R - 9R

CE_L

OE_L

UB_L

LB_L

CE_R

OE_R

UB_R

LB_R

R/W_L

R/W_R

(1,2 )

BUSY_L

BUSY_R

SEM _L

SEM _R

( 2 )

( 2)

INT_L

INT

M/S

1-F-PMK008-0001

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