AK7712A-VT

更新时间： 2024-02-23 01:15:59

品牌	Logo	应用领域
AKM		商用集成电路
页数	文件大小	规格书
87页	963K
描述
Built-in 20-bit ADC/DAC Sophisticated Audio DSP

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技术参数
数据手册

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AK7712A-VT 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LFQFP,	针数：	100
Reach Compliance Code：	unknown	风险等级：	5.84
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-PQFP-G100
长度：	14 mm	功能数量：	1
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.7 mm	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

AK7712A-VT 数据手册

ASAHI KASEI

[AK7712A-VT]

AK7712A-VT

Built-in 20-bit ADC/DAC Sophisticated Audio DSP

General Description

The AK7712A is a DSP(Digital Signal Processor) with built-in high performance 20bit 2ch ADC and 4ch DAC, on

purposeto control the sound field. It is possible to calculate 383 steps on 44.1kHz and 48kHz sampling respectively.

In case of 32kHz sampling, it can caluculate up to 511 steps. With a combination of this LSI and external memory

for delay data,it can berealized easily to control the sound field such as Echo, Surround Presence Controller, and

Key-control which are needed forsomething like Karaoke. Parametric Equalizing can be done without external

memory.

Features

[ DSP unit ]

Word length: 24-bit (data RAM)

Instruction cycle time: 54ns(maximum speed)

Multiplier: 24 × 16 → 40-bit

Divider: 16 ÷ 16 → 16-bit

Program RAM: 384 × 32 bit

External memory: DRAM,Pseudo-SRAM and SRAM can be connected (only use for delay data).

Sampling frequency: 32kHz 48kHz

Automatic clear function of external RAM:

47msec after bringing RST high at fs=48kHz (include internal data RAM)

Microcomputer interface:

synchronized signal type 8-bit serial input 1 channel,

synchronized signal type 24-bit serial output 1 channel

Master clock: 512(511)/384(383)/256(255)fs

The value inside ( ) is maximum calculation steps.

512fs mode is available when 32kHz sampling is chosen.

Conversion of master/slave mode for LRCK and BCLK:

When master mode is selected, the outputs of LRCK and BCLK depend

on the set-up for input format.

Serial input ports(2~4ch), and output ports(2~6ch) : 16/20/24 bit words

[ ADC unit ]

20-bit 64 × Oversampling ∆Σ ADC: 2ch

S/(N+D):

DR, S/N:

92dB

98dB

[ DAC unit ]

20-bit 128 × Oversampling ∆Σ DAC: 4ch

S/(N+D):

DR, S/N:

86dB

97dB

Digital HPF (fc=1Hz)

[ Total ]

Power supply: +5V

Package: 100pin LQFP(0.5mm pitch)

0180-E-02

- 1 -

1997/12

12 3 4 5 6 7...87

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