Accutek
Microcircuit
Corporation
AK632512W / AK632512Z
524,288 x 32 Bit CMOS / BiCMOS
Static Random Access Memory
DESCRIPTION
Front View
72-Pin SIM
The Accutek AK632512 SRAM Module consists of fast high perfor-
mance SRAMs mounted on a low height, 72 pin SIM or ZIP Board.
The module utilizes four 36 pin 512K x 8 SRAMs in 400 mil SOJ
packages and four decoupling capacitors mounted on the front side
of a printed circuit board.
37
72
1
36
The SRAMs used have common I/O functions and single output en-
able functions. Also, four separate chip select (CE) connections are
used to independently enable the four bytes. The modules can be
supplied in a variety of access time values from 15 nSEC to
35 nSEC in CMOS or BiCMOS technology.
72-Pin ZIP
The Accutek module is designed to have a maximum seated height
of 0.640 inch SIM or 0.555 inch ZIP to provide for the lowest height
off the board. Each conforms to JEDEC-standard sizes and pin-out
configurations. Using four pins for module memory density identifi-
cation, PD0, PD1, PD2 and PD3 minimizes interchangeability and
design considerations when changing from one module size to the
other in customer applications.
1
36
37
72
· Presence Detect, PD0, PD1, PD2 and PD3 for identifying module
density
· Downward compatible with 256K x 32 (AK632256), 128K x 32
(AK632128), 64K x 32 (AK63264) and 32K x 32 (AK63232), 64
pin SIM or ZIP designs
FEATURES
· 524,288 x 32 bit organization
· Upward compatible with 1 Meg x 32 (AK6321024)
· TTL-compatible inputs and outputs
· JEDEC Standard 72 pin SIM or ZIP format
· Common I/O, single OE and WE functions with four separate
chip selects (CE)
· Single +5 Volt (æ10%) power supply
· Operating free air temperature 00 to 700C
· Fast access times from 15 nSEC
· Low height, 0.640 inch SIM or 0.555 inch ZIP maximum
ELECTRICAL SPECIFICATIONS
· Power:
720mA Max Active (20 nSEC)
760mA Max Active (15 nSEC)
800mA Max Active (12 nSEC)
200mA Max Standby
Timing diagrams and basic electrical characteristics are those of the
standard 512K x 8 SRAMs used to construct these modules.
Accutek’s module design allows the flexibility of selecting indus-
try-compatible 512K x 8 SRAMs from several SRAM manufacturers.
PIN NOMENCLATURE
PIN ASSIGNMENT
FUNCTIONAL DIAGRAM
PIN #
1
SYMBOL
NC
PIN #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SYMBOL
A1
PIN #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SYMBOL
CE4
CE3
A17
PIN #
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SYMBOL
A5
A0 - A18
WE
+
+
A0 - A18
WE
A0 - A18
CE1 - CE4
DQ1 - DQ32
OE
Address Inputs
19
*
*
+
+
+
+
DQ1 - DQ8
DQ1 - DQ8
DQ1 - DQ8
DQ1 - DQ8
Chip Enable
Data In/Data Out
Output Enable
Presence Detect
5v Supply
2
NC
A8
A12
OE
+
+
OE
3
PD2
PD3
Vss
A2
Vcc
CE
4
A9
A16
A13
CE1
5
DQ13
DQ5
DQ14
DQ6
DQ15
DQ7
DQ16
DQ8
Vss
OE
A6
A0 - A18
WE
6
PD0
PD1
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ4
DQ12
Vcc
Vss
DQ21
DQ29
DQ22
DQ30
DQ23
DQ31
DQ24
DQ32
Vss
PD0 - PD3
Vcc
*
*
7
DQ25
DQ17
DQ26
DQ18
DQ27
DQ19
DQ27
DQ20
A3
DQ9 - DQ16
DQ17 - DQ24
DQ25 - DQ32
8
OE
Vss
Ground
9
CE
CE2
CE3
CE4
+
+
+
10
11
12
13
14
15
16
17
18
WE
Write Enable
A0 - A18
WE
*
*
MODULE OPTIONS
OE
WE
CE
Leadless SIM: AK632512W
Leaded SIP: AK632512G
Leaded ZIP: AK632512Z
A15
A14
CE2
CE1
A18
A10
NC
A0 - A168
WE
A0
A4
NC
*
*
A7
A11
NC
DQ1 - DQ8
OE
PD0
PD1
=
=
Open
Open
PD2
PD3
=
=
Vss
Open
CE