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AK59256ASW-70 PDF预览

AK59256ASW-70

更新时间: 2024-09-19 03:04:19
品牌 Logo 应用领域
ACCUTEK 动态存储器
页数 文件大小 规格书
2页 90K
描述
DRAM

AK59256ASW-70 数据手册

 浏览型号AK59256ASW-70的Datasheet PDF文件第2页 
Accutek  
Microcircuit  
Corporation  
AK59256AS / AK59256AG  
262,144 Word by 9 bit, CMOS  
Dynamic Random Access Memory  
DESCRIPTION  
Front View  
30-Pin SIM  
The Accutek AK59256A high density memory modules is a random  
access memory organized in 256K x 9 bit words. The assembly  
consists of two 256K x 4 and one 256K x 1 DRAMs in surface mount  
packages mounted to the front side of a printed circuit board. The  
module can be configured as a leadless 30 pad SIM or a leaded 30  
pin SIP. This packaging approach provides a better than 6 to 1 den-  
sity increase over standard DIP packaging.  
+
+
30  
1
30-Pin SIP  
The operation of the AK59256A is identical to two 256K x 4 DRAMs  
plus one 256K x 1 DRAM. For the lower eight bits data input is tied  
to data output and brought out separately for each 256K x 4 device,  
with common RAS, CAS and WE control. The OE pins are tied to  
Vss which dictates the use of early-write cycles to prevent conten-  
tion of D and Q. Since the Write-Enable (WE) signal must always go  
low before CAS in a write cycle, Read-Write and Read-Modify-Write  
operation is not possible. For the ninth bit, the data input (D9) and  
data output (Q9) pins are brought out separately and controlled by a  
separate PCAS for that bit. Bit nine is generally used for parity.  
+
+
1
· Power:  
FEATURES  
1.26 Watt Max Active (70 nSEC)  
1.10 Watt Max Active (80 nSEC)  
.935 Wat Max Active (100 nSEC)  
22 mWatt Standby (Max)  
· 262,144 x 9 bit organization  
· Optional 30 Pad SIM (Single In-Line Module) or 30 Pin leaded  
SIP (Single In-Line Package)  
· Operating free air temperature: 0o to 70oC  
· JEDEC standard pinout  
· Upward compatible with AK491024, AK591024, AK594096  
and AK5916384  
· Common CAS, RAS and WE control for the lower eight bits  
· Separate PCAS control for D9 and Q9  
· Functionally and Pin compatible with AK49256  
· Available with access times of 60 nSEC to 100 nSEC  
PIN NOMENCLATURE  
PIN ASSIGNMENT  
FUNCTIONAL DIAGRAM  
PIN #  
1
SYMBOL  
Vcc  
CAS  
DQ1  
A0  
PIN #  
SYMBOL  
DQ5  
A8  
DQ1 - DQ8  
D9  
Data In / Data Out  
A0 - A8  
+
A0 - A8  
RAS  
CAS  
WE  
DQ1  
DQ2  
DQ3  
DQ4  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
RAS  
CAS  
WE  
+
+
+
*
*
*
Data In  
2
3
NC  
Q9  
Data Out  
DQ1 +  
*
4
NC  
DQ2  
DQ3  
DQ4  
+
+
+
*
*
*
A0 - A9  
CAS, PCAS  
RAS  
Address Inputs  
Column Address Strobe  
Row Address Strobe  
Write Enable  
5v Supply  
5
A1  
DQ6  
WE  
OE  
OE  
Q
*
6
DQ2  
A2  
7
Vss  
DQ7  
NC  
A0 - A8  
RAS  
CAS  
WE  
DQ1  
DQ2  
DQ3  
DQ4  
8
A3  
WE  
*
*
*
9
Vss  
DQ3  
A4  
Vcc  
10  
11  
12  
13  
14  
15  
DQ8  
Q9  
DQ5 +  
*
DQ6  
DQ7  
DQ8  
+
+
+
*
*
*
Vss  
Ground  
A5  
RAS  
PCAS  
D9  
*
NC  
No Connect  
DQ4  
A6  
A0 - A8  
RAS  
CAS  
MODULE OPTIONS  
A7  
Vcc  
*
*
*
PCAS  
+
WE  
Leadless SIM: AK59256AS  
Leaded SIP: AK59256AG  
D9  
Q9  
+
+
D
*
*

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