AGR18060E
60 W, 1805 MHz—1880 MHz, LDMOS RF Power Transistor
Table 1. Thermal Characteristics
Introduction
Parameter
Thermal Resistance,
Junction to Case:
AGR18060EU
Sym
Value
Unit
The AGR18060E is a 60 W, 26 V N-channel laterally
diffused metal oxide semiconductor (LDMOS)
RF power field effect transistor (FET) suitable for
enhanced data for global evolution (EDGE), global
system for mobile communication (GSM), and single-
carrier or multicarrier class AB power amplifier appli-
cations. It is packaged in an industry-standard pack-
age and is capable of delivering a minimum output
power of 60 W, which makes it ideally suited for
today’s wireless base station RF power amplifier
applications.
1.00
1.00
°C/W
°C/W
Rı JC
Rı JC
AGR18060EF
Table 2. Absolute Maximum Ratings*
Parameter
Sym Value Unit
VDSS 65 Vdc
VGS –0.5, 15 Vdc
Drain-source Voltage
Gate-source Voltage
Total Dissipation at TC = 25 °C:
AGR18060EU
PD
PD
175
175
W
W
AGR18060EF
Derate Above 25 ˇC:
AGR18060EU
AGR18060EF
—
—
TJ
1.00
1.00
200
W/°C
W/°C
°C
AGR18060EU AGR18060EF
Figure 1. Available Packages
Operating Junction Tempera-
ture
Storage Temperature Range
TSTG –65, 150 °C
Features
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress rat-
ings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Typical EDGE performance:
1880 MHz, 26 V, IDQ = 500 mA
— Output power (POUT): 20 W.
— Power gain: 15 dB.
— Efficiency: 34%.
— Modulation spectrum:
@ ±400 kHz = –62 dBc.
@ ±600 kHz = –73 dBc.
— Error vector magnitude (EVM) = 2%.
Table 3. ESD Rating*
Minimum (V)
Class
AGR18060E
HBM
500
50
1B
A
MM
Typical performance over entire GSM band:
— P1dB: 60 W typ.
CDM
1500
4
— Power gain: @ P1dB = 14 dB.
— Efficiency @ P1dB = 52% typical.
— Return loss: –10 dB.
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
PEAK Devices
during all handling, assembly, and test operations. Agere
High-reliability, gold-metalization process.
employs both a human-body model (HBM) and a charged-device
model (CDM) qualification requirement in order to determine
ESD-susceptibility limits and protection design evaluation. ESD
voltage thresholds are dependent on the circuit parameters used
in each of the models, as defined by JEDEC's JESD22-A114
(HBM) and JESD22-C101 (CDM) standards.
Low hot carrier injection (HCI) induced bias drift
over 20 years.
Internally matched.
Caution: MOS devices are susceptible to damage from elec-
trostatic charge. Reasonable precautions in han-
dling and packaging MOS devices should be
observed.
High gain, efficiency, and linearity.
Integrated ESD protection.
Device can withstand 10:1 voltage standing wave
ratio (VSWR) at 26 Vdc, 1805 MHz, 60 W continu-
ous wave (CW) output power.
Large signal impedance parameters available.