Datasheet > AGLN030V2-FUCG81

AGLN030V2-FUCG81

更新时间： 2024-11-27 14:19:59

品牌	Logo	应用领域
美高森美 - MICROSEMI		栅可编程逻辑
页数	文件大小	规格书
114页	3991K
描述
Field Programmable Gate Array, PBGA81, 4 X 4 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, UCSP-81

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技术参数
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AGLN030V2-FUCG81 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.79	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B81	端子数量：	81
封装主体材料：	PLASTIC/EPOXY	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
表面贴装：	YES	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

AGLN030V2-FUCG81 数据手册

Advance v0.4

IGLOO nano Low-Power Flash FPGAs

with Flash*Freeze Technology

Advanced I/Os

Features and Benefits

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

Low Power

• nanoPower Consumption—Industry’s Lowest Power

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

Mode

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

Small Footprint Packages

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• As Small as 3x3 mm in Size

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL^†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

• Retains Programmed Design When Powered Off

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

†

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except × 18 organization)

to Secure FPGA Contents

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

Enhanced Commercial Temperature Range

• –20°C to +70°C

• Segmented, Hierarchical Routing and Clock Structure

IGLOO nano Devices

AGLN010 AGLN015 AGLN020

AGLN030

AGLN060

60 k

512

1,536

AGLN125

125 k

1,024

3,072

AGLN250

250 k

2,048

6,144

System Gates

10 k

260

15 k

128

384

20 k

172

520

30 k

256

768

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

–

4,608-Bit Blocks

–

FlashROM Bits

1 k

–

1 k

–

1 k

–

1 k

–

1 k

Yes

1 k

Secure (AES) ISP

Yes

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

–

Maximum User I/Os (Known Good Die)

Package Pins

UC/CS

QFN

UC36

QN48

UC81, CS81 UC81, CS81

CS81

QN100

VQ100

CS81

QN100

VQ100

CS81

QN100

VQ100

QN68

QN48, QN68

VQ100

VQFP

Notes:

1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer

to "IGLOO nano Ordering Information" on page III.

2. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. AGLN030 and smaller devices do not support this

feature.

3. Six chip (main) and three quadrant global networks are available for AGLN060 and above.

4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe handbooks.

† AGLN030 and smaller devices do not support this feature.

December 2008

12 3 4 5 6 7...114

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与AGLN030V2-FUCG81相关器件

型号	品牌	获取价格	描述	数据表
AGLN030V2-QN100	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100ES	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100I	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100PP	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100Y	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100YES	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100YI	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN100YPP	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN81	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN030V2-QN81ES	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology

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