Datasheet > AGLE30005-FGG896YC

AGLE30005-FGG896YC

更新时间： 2024-11-11 15:45:19

品牌	Logo	应用领域
美高森美 - MICROSEMI		可编程逻辑
页数	文件大小	规格书
164页	8577K
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FPGA

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技术参数
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AGLE30005-FGG896YC 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.74	JESD-609代码：	e1
湿度敏感等级：	3	峰值回流温度（摄氏度）：	250
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
处于峰值回流温度下的最长时间：	40	Base Number Matches：	1

AGLE30005-FGG896YC 数据手册

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Revision 12

IGLOOe Low Power Flash FPGAs

with Flash*Freeze Technology

•

Bank-Selectable I/O Voltages—Up to 8 Banks per Chip

Features and Benefits

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

Low-Power Active FPGA Operation

•

Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

I/O Registers on Input, Output, and Enable Paths

Hot-Swappable and Cold-Sparing I/Os

Flash*Freeze

Technology

Enables

Ultra-Low

Power

Consumption while Maintaining FPGA Content

Flash*Freeze Pin Allows Easy Entry to / Exit from Ultra-Low-

Power Flash*Freeze Mode

•

High Capacity

•

600 k to 3 Million System Gates

108 to 504 kbits of True Dual-Port SRAM

Up to 620 User I/Os

•

Programmable Output Slew Rate and Drive Strength

Programmable Input Delay

Schmitt Trigger Option on Single-Ended Inputs

Weak Pull-Up/-Down

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

•

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the IGLOO e Family

Retains Programmed Design when Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

Clock Conditioning Circuit (CCC) and PLL

•

Six CCC Blocks, Each with an Integrated PLL

Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

In-System Programming (ISP) and Security

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

•

Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

•

FlashLock Designed to Secure FPGA Contents

1 kbit of FlashROM User Nonvolatile Memory

High-Performance Routing Hierarchy

SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)

True Dual-Port SRAM (except ×18)

•

Segmented, Hierarchical Routing and Clock Structure

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

•

ARM Processor Support in IGLOOe FPGAs

•

Pro (Professional) I/O

M1 IGLOOe Devices—Cortex™-M1 Soft Processor Available

with or without Debug

•

700 Mbps DDR, LVDS-Capable I/Os

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Table 1 • IGLOOe Product Family

IGLOOe Devices

AGLE600

AGLE3000

ARM-Enabled IGLOOe Devices

System Gates

M1AGLE3000

600,000

13,824

3,000,000

VersaTiles (D-flip-flops)

Quiescent Current (typical) in Flash*Freeze Mode (µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

75,264

137

504

112

108

FlashROM Kbits (1,024 bits)

Secure (AES) ISP

Yes

CCCs with Integrated PLLs

VersaNet Globals ¹

I/O Banks

Maximum User I/Os

270

620

Package Pins

FBGA

FG256, FG484

FG484, FG896

Notes:

1. Refer to the Cortex-M1 Handbook for more information.

2. Six chip (main) and twelve quadrant global networks are available.

3. For devices supporting lower densities, refer to the IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology datasheet.

September 2012

12 3 4 5 6 7...164

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与AGLE30005-FGG896YC相关器件

型号	品牌	获取价格	描述	数据表
AGLE30005-FGG896YI	MICROSEMI	获取价格	FPGA
AGLE3000-FGG484	MICROSEMI	获取价格	暂无描述
AGLE3000V2-FFG484C	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23
AGLE3000V2-FFG484I	ACTEL	获取价格	Field Programmable Gate Array, 3000000 Gates, 250MHz, CMOS, PBGA484, 23 X 23 MM, 1 MM PITC
AGLE3000V2-FFG896	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFG896C	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA896, 31 X 31 MM, 2.23
AGLE3000V2-FFG896ES	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFG896I	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFG896PP	ACTEL	获取价格	IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FFGG484C	MICROSEMI	获取价格	Field Programmable Gate Array, 75264 CLBs, 3000000 Gates, CMOS, PBGA484, 23 X 23 MM, 2.23

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