Revision 2
Extended Temperature Fusion Family of Mixed Signal FPGAs
•
6 Clock Conditioning Circuits (CCCs) with 2 Integrated PLLs
Features and Benefits
–
–
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
Extended Temperature Tested
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Each Device Tested from –55°C to 100°C Junction Temperature
Low Power Consumption
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High-Performance Reprogrammable Flash Technology
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low-Power Modes
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Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Instant On Single-Chip Solution
In-System Programming (ISP) and Security
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•
ISP with 128-Bit AES via JTAG
350 MHz System Performance
FlashLock® Designed to Secure FPGA Contents
Embedded Flash Memory
Advanced Digital I/O
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User Flash Memory – 4 Mbits to 8 Mbits
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1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
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Configurable 16- or 32-Bit Datapath
10 ns Access in Read-Ahead Mode
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1 Kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
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•
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Up to 12-Bit Resolution and Up to 600 Ksps
Internal 2.56 V or External Reference Voltage
ADC: 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor† and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
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Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS
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Built-In I/O Registers
700 Mbps DDR Operation
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Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Pull-Down Resistor
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Pin-Compatible Packages across the Fusion® Family
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P- and N-Channel Power MOSFET Support
Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths
SRAMs and FIFOs
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ADC Accuracy Is Better than 1%
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and
×18 organizations available)
On-Chip Clocking Support
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Internal 100 MHz RC Oscillator (Accurate to 1%)
Crystal Oscillator Support (32 KHz to 20 MHz)
Programmable Real-Time Counter (RTC)
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True Dual-Port SRAM (except ×18)
Programmable Embedded FIFO Control Logic
Soft ARM® Cortex™- M1 Fusion Devices (M1)
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ARM Cortex-M1–Enabled
Table 1 • Fusion Extended Temperature Devices
Fusion Devices
AFS600
AFS1500
*
ARM Cortex-M1 Devices
M1AFS600
M1AFS1500
System Gates
600,000
13,824
Yes
2
1,500,000
38,400
Yes
2
Tiles (D-flip-flops)
General Information
Secure (AES) ISP
PLLs
Globals
18
18
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
FlashROM Bits
2
4
4M
1,024
24
8M
Memory
1,024
60
RAM Blocks (4,608 bits)
RAM kbits
108
10
270
10
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
30
30
10
10
Analog and I/Os
5
5
172
40
223
40
Note: *Refer to the Cortex-M1 product brief for more information.
† Refer to Table 2 on page IV for details.
January 2013
I
© 2013 Microsemi Corporation
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