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AFE7700IALK PDF预览

AFE7700IALK

更新时间: 2024-09-20 02:51:59
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
12页 409K
描述
AFE7700 Quad-Channel General Purpose RF Transceiver

AFE7700IALK 数据手册

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AFE7700  
SLOSE44A OCTOBER 2019REVISED MARCH 2020  
AFE7700 Quad-Channel General Purpose RF Transceiver  
1 Features  
3 Description  
The AFE7700 device is  
a
high-performance,  
1
Quad transmitters based on direct up-conversion  
architecture:  
multichannel transceiver, integrating four direct up-  
conversion transmitter chains, four direct down-  
conversion receiver chains, and two wideband RF  
sampling digitizing auxiliary chains (feedback paths).  
The high dynamic range of the transmitter and  
receiver chains enables high performance wireless  
transceiver systems.  
Up to 600 MHz of RF transmitted bandwidth  
per chain  
Quad receivers based on 0-IF down-conversion  
architecture:  
Up to 200 MHz of RF received bandwidth per  
chain  
The low power dissipation and large channel  
integration of the AFE7700 allows the device to  
address the power and size constraints of multi-  
antenna and phased array systems. The wideband  
and high dynamic range feedback path can assist the  
Digital Pre-Distortion (DPD) of power amplifiers and  
IQ correction in the transmitter chain. The fast  
SerDes speed can reduce the number of lanes  
required to transfer the data in and out.  
Feedback chain based on RF sampling ADC:  
Up to 600 MHz of RF received bandwidth  
RF frequency range: 600 MHz to 6 GHz  
Four wideband fractional-N PLL, VCO for TX and  
RX LO  
Dedicated integer-N PLL, VCO for data converters  
clock generation  
Device Information(1)  
JESD204B and JESD204C SerDes interface  
support:  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
8 SerDes transceivers up to 29.5 Gbps  
8b/10b and 64b/66b encoding  
AFE7700  
FCBGA (400)  
17.00 mm × 17.00 mm  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
16-bit, 12-bit, 24-bit and 32-bit formatting  
Subclass 1 multi-device synchronization  
AFE7700 Block Diagram  
Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch  
2 Applications  
RF PLL 3  
LO  
Dist  
VDD1p2TX  
Phased Array Radar  
PLL-VCO  
VSSTX  
TX Chain 1  
1SRX  
1STX  
Defense Radio  
DAC  
1TX+/-  
2SRX  
2STX  
Wireless Communications Test  
Vector Signal Transceiver (VST)  
Electronic Warfare  
VDD1p8TX  
VSSTX  
TX Chain 2  
DAC  
2TX+/-  
3SRX  
3STX  
SYSREF  
TX DIG  
TX DIG  
From  
SPI  
4SRX  
REFCLK_+/  
-
4STX  
VDD1p8PLL  
VSSPLL  
Common Dig  
Syncbin/out  
5SRX  
5STX  
TX Chain 4  
TX DIG  
TX DIG  
DAC  
3TX+/-  
6SRX  
6STX  
From  
SPI  
TX Chain 3  
VDD1p8TX  
VSSTX  
DAC  
7SRX  
7STX  
4TX+/-  
VDD1p2TX  
VSSTX  
From SPI  
8SRX  
8STX  
MCU  
GPIO  
GPIOs  
RF PLL 4  
Config  
LO  
Dist  
PLL-VCO  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 

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