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AFE2124EG4 PDF预览

AFE2124EG4

更新时间: 2024-11-07 21:12:43
品牌 Logo 应用领域
德州仪器 - TI 电信光电二极管电信集成电路
页数 文件大小 规格书
15页 343K
描述
DATACOM, DIGITAL SLIC, PDSO48, PLASTIC, SSOP-48

AFE2124EG4 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69数据速率:1168 Mbps
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:15.875 mm湿度敏感等级:2
功能数量:1端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP48,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3/5,5 V认证状态:Not Qualified
座面最大高度:2.79 mm子类别:Other Telecom ICs
标称供电电压:3.3 V表面贴装:YES
技术:CMOS电信集成电路类型:DIGITAL SLIC
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

AFE2124EG4 数据手册

 浏览型号AFE2124EG4的Datasheet PDF文件第2页浏览型号AFE2124EG4的Datasheet PDF文件第3页浏览型号AFE2124EG4的Datasheet PDF文件第4页浏览型号AFE2124EG4的Datasheet PDF文件第5页浏览型号AFE2124EG4的Datasheet PDF文件第6页浏览型号AFE2124EG4的Datasheet PDF文件第7页 
®
AFE2124  
AFE2124  
For most current data sheet and other product  
information, visit www.burr-brown.com  
Dual HDSL/SDSL ANALOG FRONT END  
FEATURES  
SERIAL DIGITAL INTERFACE  
DESCRIPTION  
Burr-Brown’s dual Analog Front End chip greatly re-  
duces the size and cost of a DSL (Digital Subscriber  
Line) system by providing all of the active analog  
circuitry needed to connect two digital signal processors  
to external compromise hybrids and line transformers.  
The AFE2124 is optimized for HDSL (High bit rate  
DSL) and for SDSL (symmetrical DSL) applications.  
Because the transmit and receive filter responses auto-  
matically change with clock frequency, the AFE2124 is  
particularly suitable for multiple rate DSL systems. The  
device operates over a wide range of data rates from  
64kbps to 1168kbps.  
48-LEAD SSOP PACKAGE  
E1, T1 AND SDSL OPERATION  
64kbps TO 1168kbps OPERATION  
SCALEABLE DATA RATE  
250mW POWER DISSIPATION PER  
CHANNEL  
TWO COMPLETE HDSL ANALOG INTER-  
FACES  
+5V POWER (5V or 3.3V Digital)  
Functionally, each half of this unit consists of a transmit  
and a receive section. The transmit section generates  
analog signals from 2-bit digital symbol data and filters  
the analog signals to create 2B1Q symbols. The on-  
board differential line driver provides a 13.5dBm signal  
to the telephone line. The receive section filters and  
digitizes the symbol data received on the telephone line.  
This IC operates on a single 5V supply. The digital  
circuitry in the unit can be connected to a supply from  
3.3V to 5V. It is housed in a 48-lead SSOP package.  
txLINE  
Pulse Former  
txLINE  
Line Driver  
tx and rx  
Control  
Registers  
tx and rx  
Interface  
Lines  
Difference  
Amplifier  
rxHYB  
rxHYB  
rxLINE  
Decimation  
Filter  
∆Σ  
Modulator  
rxLINE  
Programmable  
Gain Amp  
1/2 of AFE2124  
Patents Pending  
International Airport Industrial Park  
Mailing Address: PO Box 11400, Tucson, AZ 85734  
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706  
• Tel: (520) 746-1111  
Twx: 910-952-1111  
Internet: http://www.burr-brown.com/  
Cable: BBRCORP Telex: 066-6491  
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132  
©1999 Burr-Brown Corporation  
PDS-1538A  
Printed in U.S.A. April, 1999  
SBWS010  

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