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ADV202BBCZ-115 PDF预览

ADV202BBCZ-115

更新时间: 2024-11-04 22:05:23
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页数 文件大小 规格书
40页 1018K
描述
JPEG2000 Video Codec

ADV202BBCZ-115 数据手册

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JPEG2000 Video Codec  
ADV202  
FEATURES  
APPLICATIONS  
Complete single-chip JPEG2000 compression and  
decompression solution for video and still images  
Patented SURF™ (spatial ultraefficient recursive filtering)  
technology enables low power and low cost wavelet based  
compression  
Supports both 9/7 and 5/3 wavelet transforms with up to  
6 levels of transform  
Programmable tile/image size with widths up to 2048 pixels  
in 3-component 4:2:2 interleaved mode, and up to  
4096 pixels in single-component mode  
Networked video and image distribution systems  
Wireless video and image distribution  
Image archival/retrieval  
Digital CCTV and surveillance systems  
Digital cinema systems  
Professional video editing and recording  
Digital still cameras  
Digital camcorders  
Maximum tile/image height: 4096 pixels  
GENERAL DESCRIPTION  
Video interface directly supporting ITU.R-BT656,  
SMPTE125M PAL/ NTSC, SMPTE274M, SMPTE293M (525p),  
ITU.R-BT1358 (625p) or any video format with a maximum  
input rate of 65 MSPS for irreversible mode or 40 MSPS for  
reversible mode  
Two or more ADV202s can be combined to support full-  
frame SMPTE274M HDTV (1080i) or SMPTE296M (720p)  
Interlaces temporally coherent frame-based SD video  
sources for improved performance  
Flexible asynchronous SRAM-style host interface allows  
glueless connection to most 16-/32-bit microcontrollers  
and ASICs  
The ADV202 is a single-chip JPEG2000 codec targeted for  
video and high bandwidth image compression applications that  
can benefit from the enhanced quality and feature set provided  
by the JPEG2000 (J2K)—ISO/IEC15444-1 image compression  
standard. The part implements the computationally intensive  
operations of the JPEG2000 image compression standard as  
well as providing fully compliant code-stream generation for  
most applications.  
The ADV202s dedicated video port provides glueless  
connection to common digital video standards such as ITU.R-  
BT656, SMPTE125M, SMPTE293M [525p], ITU.R-BT1358  
[625p], SMPTE274M[1080i], or SMPTE296M[720p]. A variety  
of other high speed synchronous pixel and video formats can  
also be supported using the programmable framing and  
validation signals.  
2.5 V to 3.3 V I/O and 1.5 V core supply  
12 mm × 12 mm 121-lead CSPBGA, speed grade 115 MHz, or  
13 mm × 13 mm 144-lead CSPBGA, speed grade 150 MHz  
(continued on Page 3)  
FUNCTIONAL BLOCK DIAGRAM  
ADV202  
WAVELET  
ENGINE  
EC1  
EC2  
EC3  
PIXEL I/F  
PIXEL I/F  
HOST I/F  
EXTERNAL  
DMA CTRL  
PIXEL  
FIFO  
INTERNAL BUS AND DMA ENGINE  
CODE  
FIFO  
ATTRIBUTE  
FIFO  
EMBEDDED RISC  
MEMORY  
PROCESSOR  
SYSTEM  
ANCILLARY  
FIFO  
SYSTEM  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.326.8703  
www.analog.com  
© 2004 Analog Devices, Inc. All rights reserved.  

ADV202BBCZ-115 替代型号

型号 品牌 替代类型 描述 数据表
ADV202BBC-115 ADI

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