3.75 kV, 6-Channel, SPIsolator Digital
Isolator for SPI with Delay Clock
Data Sheet
ADuM3150
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Supports up to 40 MHz SPI clock speed in delay clock mode
Supports up to 17 MHz SPI clock speed in 4-wire mode
4 high speed, low propagation delay, SPI signal isolation
channels
2 data channels at 250 kbps
Delayed compensation clock line
20-lead SSOP with 5.1 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
V
1
20
V
DD1
DD2
ADuM3150
ENCODE
GND
GND
2
19
1
2
DECODE
DECODE
ENCODE
DECODE
MCLK
MO
3
18 SCLK
ENCODE
SI
4
17
16
15
14
13
12
11
DECODE
SO
SSS
MI
5
ENCODE
MSS
6
V
V
7
IA
OA
CONTROLꢀ
BLOCK
CONTROL
BLOCK
V
V
8
OB
IB
DCLK
NIC
9
CLK
DELAY
UL recognition per UL 1577
GND
GND
1
10
2
3750 V rms for 1 minute
CSA Component Acceptance Notice 5A
VDE certificate of conformity
Figure 1.
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM = 565 V peak
APPLICATIONS
Industrial programmable logic controllers (PLC)
Sensor isolation
GENERAL DESCRIPTION
The ADuM31501 is a 6-channel SPIsolator™ digital isolator
optimized for isolated serial peripheral interfaces (SPIs). Based
on the Analog Devices, Inc., iCoupler® chip scale transformer
technology, the low propagation delay in the CLK, MO/SI,
Table 1. Related Products
Product
Description
ADuM3151/ADuM3152/
ADuM3153
ADuM3154
ADuM4150
3.75 kV, multichannel SPI isolator
SS
MI/SO, and SPI bus signals supports SPI clock rates of up to
3.75 kV, multiple slave SPI isolator
5 kV, high speed, clock delayed
SPIsolator
17 MHz. These channels operate with 14 ns propagation delay
and 1 ns jitter to optimize timing for SPI.
ADuM4151/ADuM4152/
ADuM4153
ADuM4154
5 kV, multichannel SPI isolator
The ADuM3150 isolator also provides two additional independent
low data rate isolation channels, one channel in each direction.
Data in the slow channels is sampled and serialized for a 250 kbps
data rate with 2.5 µs of jitter.
5 kV, multiple slave SPI isolator
The ADuM3150 supports a delay clock output on the master
side of the device. This output can be used with an additional
clocked port on the master to support 40 MHz clock performance.
See the Delay Clock section for more information.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. A
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