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ADSP-BF538BBCZ-5A

更新时间： 2024-11-27 04:48:55
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
56页 3080K
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Blackfin Embedded Processor

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Blackfin®  
Embedded Processor  
a
Preliminary Technical Data  
FEATURES  
Up to 500 MHz high performance Blackfin processor  
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,  
40-bit shifter  
ADSP-BF538/ADSP-BF538F  
Memory management unit providing memory protection  
External memory controller with glueless support  
for SDRAM, SRAM, flash, and ROM  
Flexible memory booting options from SPI® and external  
memory  
RISC-like register and instruction model for ease of pro-  
gramming and compiler friendly support  
PERIPHERALS  
Advanced debug, trace, and performance monitoring  
0.8 V to 1.2 V core VDD with on-chip voltage regulation  
3.3 V tolerant I/O with specific 5 V tolerant pins  
316-ball Pb-free mini-BGA package  
Parallel peripheral interface (PPI/GPIO)  
supporting ITU-R 656 video data formats  
Four dual-channel, full-duplex synchronous serial ports, sup-  
porting 16 stereo I2S® channels  
Two DMA controllers supporting 26 DMA channels  
Controller area network (CAN) 2.0B controller  
Three SPI-compatible ports  
Three timer/counters with PWM support  
Three UARTs with support for IrDA®  
Two TWI controllers compatible with I2C® industry standard  
Up to 54 general-purpose I/O pins (GPIO)  
Real time clock, watchdog timer, and core timer  
On-chip PLL capable of 0.5x To 64x frequency multiplication  
Debug/JTAG interface  
MEMORY  
148K bytes of on-chip memory:  
16K bytes of instruction SRAM/cache  
64K bytes of instruction SRAM  
32K bytes of data SRAM  
32K bytes of data SRAM/cache  
4K bytes of scratchpad SRAM  
512K bytes or 1M byte of flash memory (ADSP-BF538F parts  
only)  
Four dual-channel memory DMA controllers  
JTAG TEST AND EMULATION  
VOLTAGE REGULATOR  
INTERRUPT  
WATCHDOG  
CONTROLLER  
TIMER  
B
TWI0-1  
RTC  
CAN 2.0B  
GPIO  
PORT  
C
L1  
L1  
DATA  
MEMORY  
PPI  
GPIO  
SPI1-2  
INSTRUCTION  
MEMORY  
GPIO  
PORT  
F
TIMER0-2  
SPI0  
DMA CORE  
BUS 1  
DMA ACCESS  
BUS 1  
GPIO  
PORT  
D
DMA ACCESS  
BUS 0  
DMA CORE  
BUS 0  
UART1-2  
UART0  
SPORT0-1  
DMA  
CONTROLLER1  
GPIO  
PORT  
E
EXTERNAL PORT  
FLASH, SDRAM CONTROL  
DMA  
CONTROLLER0  
SPORT2-3  
DMA  
EXTERNAL  
BUS 1  
DMA  
EXTERNAL  
BUS 0  
512 KB OR 1 MB  
FLASH MEMORY  
BOOT ROM  
(ADSP-BF538F ONLY)  
Figure 1. Functional Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. PrD  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  
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ADSP-BF538BBCZ-5A 替代型号

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ADSP-BF538BBCZ-5F4 ADI

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 Blackfin Embedded Processor

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