Datasheet > ADSP-21569-BCZ10ENG

ADSP-21569-BCZ10ENG

更新时间： 2024-09-26 03:58:47

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
95页	2059K
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Digital Signal Processor

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数据手册

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SHARC+ Single Core

High Performance DSP (up to 1 GHz)

Preliminary Technical Data

ADSP-21562/21563/21565/21566/21567/21569

SYSTEM FEATURES

MEMORY

Enhanced SHARC+ high performance floating-point core

Up to 1 GHz

Large on-chip Level 2 (L2) SRAM with ECC protection, up to

1 MB

One Level 3 (L3) interface optimized for low system power,

providing 16-bit interface to DDR3 (supporting 1.35 V

capable DDR3L devices) SDRAM devices

Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity

(optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed point

ADDITIONAL FEATURES

Byte, short-word, word, long-word addressed

Powerful DMA system

On-chip memory protection

Integrated safety features

17 mm × 17 mm 400 CSP_BGA (0.8 mm pitch), RoHS

compliant

Security and Protection

Crypto hardware accelerators

Fast secure boot with IP protection

Enhanced FIR and IIR accelerators running up to 1 GHz

APPLICATIONS

120-lead LQFP_EP (0.4 mm pitch), RoHS compliant

Low system power across automotive temperature range

Automotive: audio amplifier, head unit, ANC/RNC, rear seat

entertainment, digital cockpit, ADAS

Consumer: speakers, sound bars, AVRs, conferencing sys-

tems, mixing consoles, microphone arrays, headphones

SYSTEM CONTROL

SHARC+ CORE

SECURITY AND PROTECTION

UP TO

1 GHz

SYSTEM PROTECTION UNIT (SPU)

FLOATING-POINT

DSP

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

PERIPHERALS

FAULT MANAGEMENT (FMU)

SIGNAL ROUTING UNIT (SRU)

2×2 PRECISION CLOCK

L1 SRAM (PARITY)

DUAL CRC (WITH MemDMA)

WATCHDOGS

Up to 5 Mb (640 kB)

SRAM/CACHE

GENERATORS

2x DAI

2×4 ASRC

PAIRS

FULL SPORT

2×4

OTP MEMORY

2x PIN

BUFFER

24–28

THERMAL MONITOR UNIT (TMU)

2×1 S/PDIF Rx/Tx

PROGRAM FLOW

6× I²C

SYSTEM EVENT CONTROLLER

(SEC)

SYSTEM CROSSBAR AND DMA SUBSYSTEM

1× SPI + 2× QUAD SPI +

1× OCTAL SPI

TRIGGER ROUTING UNIT (TRU)

3× UARTs

2× LINK PORTS

22–40

CLOCK, RESET, AND POWER

CLOCK GENERATION UNIT (CGU)

L3 MEMORY

INTERFACES

SYSTEM

L2 MEMORY

SYSTEM

ACCELERATION

10× TIMERS + 1× COUNTER

MLB 3-PIN

CLOCK DISTRIBUTION UNIT (CDU)

RESET CONTROL UNIT (RCU)

DSP FUNCTIONS

(FIR, IIR)

DDR3/DDR3L

BGA ONLY

SRAM

(ECC)

UP TO 8 Mb (1 MB)

HADC (4 CHAN, 12-BIT)

DYNAMIC POWER MANAGEMENT

(DPM)

2–4

ENCRYPTION/

DECRYPTION

DEBUG UNIT

DATA

ARM CoreSight

DEBUG AND TRACE

SYSTEM WATCHPOINT UNIT

(SWU)

Figure 1. Processor Block Diagram

SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. PrE Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

12 3 4 5 6 7...95

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与ADSP-21569-BCZ10ENG相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21569KBCZ10	ADI	获取价格	SHARC Single Core High Performance DSP (Up to 1 GHz)
ADSP-21569KBCZ8	ADI	获取价格	SHARC Single Core High Performance DSP (Up to 1 GHz)
ADSP-21569WCBCZ10	ADI	获取价格	Digital Signal Processor
ADSP-21569WCBCZ8	ADI	获取价格	SHARC Single Core High Performance DSP (Up to 1 GHz)
ADSP-21569WCBCZ8RL	ADI	获取价格	SHARC Single Core High Performance DSP (Up to 1 GHz)
ADSP-21571	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-21571BSWZ-4	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-21571BSWZ-5	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-21571CSWZ-4	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5
ADSP-21571CSWZ-5	ADI	获取价格	SHARC Dual-Core DSP with ARM Cortex-A5

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