SHARC+ Single Core
High Performance DSP (Up to 1 GHz)
ADSP-21562/21563/21565/21566/21567/21569
SYSTEM FEATURES
MEMORY
Enhanced SHARC+ high performance floating-point core
Up to 1 GHz
Large on-chip Level 2 (L2) SRAM with ECC protection, up to
8 Mb (1 MB)
One Level 3 (L3) interface optimized for low system power,
providing 16-bit interface to DDR3/DDR3L SDRAM devices
5 Mb (640 kB) Level 1 (L1) SRAM memory with parity
(optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short word, word, long word addressed
Powerful DMA system
On-chip memory protection
Integrated safety features
17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS
compliant
ADDITIONAL FEATURES
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Enhanced FIR and IIR accelerators running up to 1 GHz
AEC-Q100 qualified for automotive applications
APPLICATIONS
120-lead LQFP_EP (0.4 mm pitch), RoHS compliant
Low system power across automotive temperature range
Automotive: audio amplifier, head unit, ANC/RNC, rear seat
entertainment, digital cockpit, ADAS
Consumer: speakers, sound bars, AVRs, conferencing sys-
tems, mixing consoles, microphone arrays, headphones
SYSTEM CONTROL
SECURITY AND PROTECTION
SHARC+ CORE
SYSTEM PROTECTION UNIT (SPU)
UP TO
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
1 GHz
FLOATING-POINT
DSP
S
ENCRYPTION/DECRYPTION
FAULT MANAGEMENT (FMU)
PERIPHERALS
ACCELERATORS
SIGNAL ROUTING UNIT (SRU)
FIR
IIR
2×2 PRECISION CLOCK
GENERATORS
DUAL CRC (WITH MemDMA)
WATCHDOGS
L1 SRAM (PARITY)
(UP TO (UP TO
1 GHz) 1 GHz)
5 Mb (640 kB)
SRAM/CACHE
2x DAI
2x PIN
2×4 ASRC
PAIRS
FULL SPORT
2×4
OTP MEMORY
BUFFER
24–28
THERMAL MONITOR UNIT (TMU)
2×1 S/PDIF Rx/Tx
6× I2C
PROGRAM FLOW
SYSTEM EVENT CONTROLLER
(SEC)
SYSTEM CROSSBAR AND DMA SUBSYSTEM
1× SPI + 2× QUAD SPI +
1× OCTAL SPI
G
P
I
TRIGGER ROUTING UNIT (TRU)
3× UARTs
2× LINK PORTS
22–40
O
CLOCK, RESET, AND POWER
L3 MEMORY
INTERFACES
SYSTEM
L2 MEMORY
CLOCK GENERATION UNIT (CGU)
10× TIMERS + 1× COUNTER
MLB 3-PIN
CLOCK DISTRIBUTION UNIT (CDU)
RESET CONTROL UNIT (RCU)
DDR3/DDR3L
BGA ONLY
SRAM
(ECC)
UP TO 8 Mb (1 MB)
HADC (4 CHAN, 12-BIT)
2–4
DYNAMIC POWER MANAGEMENT
(DPM)
16
DEBUG UNIT
DATA
TM
®
Arm CoreSight
DEBUG AND TRACE
SYSTEM WATCHPOINT UNIT
(SWU)
Figure 1. ADSP-21569 (Full-Featured Model) Processor Block Diagram
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