a
Low Cost DSP Microcomputers
ADSP-2104/ADSP-2109
FUNCTIO NAL BLO CK D IAGRAM
SUMMARY
16-Bit Fixed-Point DSP Microprocessors w ith
On-Chip Mem ory
Enhanced Harvard Architecture for Three-Bus
Perform ance: Instruction Bus & Dual Data Buses
Independent Com putation Units: ALU, Multiplier/
Accum ulator, and Shifter
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
DAG 2
DAG 1
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
Single-Cycle Instruction Execution & Multifunction
Instructions
DATA MEMORY ADDRESS
On-Chip Program Mem ory RAM or ROM
& Data Mem ory RAM
Integrated I/ O Peripherals: Serial Ports and Tim er
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
DATA
BUS
FEATURES
20 MIPS, 50 ns Maxim um Instruction Rate
Separate On-Chip Buses for Program and Data Mem ory
Program Mem ory Stores Both Instructions and Data
(Three-Bus Perform ance)
TIMER
ARITHMETIC UNITS
MAC SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
ALU
ADSP-2100 CORE
Dual Data Address Generators w ith Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing w ith Zero-Overhead
Looping: Single-Cycle Loop Setup
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory (e.g., EPROM )
Double-Buffered Serial Ports w ith Com panding Hardw are,
Autom atic Data Buffering, and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Pow er IDLE Instruction
T he ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 can perform all
of the following operations:
•
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
Receive and transmit data via one or two serial ports
PLCC Package
GENERAL D ESCRIP TIO N
T he ADSP-2104 and ADSP-2109 processors are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. T he
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture—
computation units, data address generators, and program
sequencer—with differentiating features such as on-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.
T he ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
T he ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.
T he ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.
T he ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. T he ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
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