a
DSP Microcomputer
ADSP-21065L
SUMMARY
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I2S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
DUAL-PORTED SRAM
CORE PROCESSOR
JTAG
7
INSTRUCTION
CACHE
TWO INDEPENDENT
DUAL-PORTED BLOCKS
TEST &
EMULATION
PROCESSOR PORT
ADDR DATA
ADDR DATA
I/O PORT
DATA ADDR
ADDR
DATA
EXTERNAL
PORT
DAG1
DAG2
PROGRAM
SEQUENCER
SDRAM
INTERFACE
IOD
48
IOA
17
PM ADDRESS BUS
DM ADDRESS BUS
24
32
24
32
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
PM DATA BUS
48
BUS
CONNECT
(PX)
DATA BUS
MUX
40 DM DATA BUS
HOST PORT
4
DMA
DATA
IOP
REGISTERS
(MEMORY MAPPED)
CONTROLLER
REGISTER
FILE
(2 Rx, 2Tx)
BARREL
SHIFTER
SPORT 0
MULTIPLIER
ALU
CONTROL,
STATUS, TIMER
&
2
(I S)
(2 Rx, 2Tx)
DATA BUFFERS
SPORT 1
2
(I S)
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000