Datasheet > ADSP-21065

ADSP-21065

更新时间： 2024-11-26 23:04:19

品牌	Logo	应用领域
亚德诺 - ADI		电脑
页数	文件大小	规格书
44页	329K
描述
DSP Microcomputer

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中文翻译

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数据手册

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ADSP-21065 数据手册

DSP Microcomputer

ADSP-21065L

SUMMARY

SDRAM Controller for Glueless Interface to Low Cost

External Memory (@ 66 MHz)

High Performance Signal Computer for Communica-

tions, Audio, Automotive, Instrumentation and

Industrial Applications

64M Words External Address Range

12 Programmable I/O Pins and Two Timers with Event

Capture Options

Code-Compatible with ADSP-2106x Family

208-Lead MQFP or 196-Ball Mini-BGA Package

3.3 Volt Operation

Super Harvard Architecture Computer (SHARC^®)

Four Independent Buses for Dual Data, Instruction,

and I/O Fetch on a Single Cycle

32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-

Point Arithmetic

Flexible Data Formats and 40-Bit Extended Precision

32-Bit Single-Precision and 40-Bit Extended-Precision IEEE

Floating-Point Data Formats

32-Bit Fixed-Point Data Format, Integer and Fractional,

with Dual 80-Bit Accumulators

544 Kbits On-Chip SRAM Memory and Integrated I/O

Peripheral

I²S Support, for Eight Simultaneous Receive and Trans-

mit Channels

KEY FEATURES

66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained

Performance

User-Configurable 544 Kbits On-Chip SRAM Memory

Two External Port, DMA Channels and Eight Serial

Port, DMA Channels

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel with

Dual Memory Read/Writes and Instruction Fetch

Multiply with Add and Subtract for Accelerated FFT But-

terfly Computation

1024-Point Complex FFT Benchmark: 0.274 ms (18,221

Cycles)

DUAL-PORTED SRAM

CORE PROCESSOR

JTAG

INSTRUCTION

CACHE

48 BIT

TWO INDEPENDENT

DUAL-PORTED BLOCKS

TEST &

EMULATION

PROCESSOR PORT

ADDR DATA

I/O PORT

DATA ADDR

ADDR

DATA

EXTERNAL

PORT

DAG1

DAG2

PROGRAM

SEQUENCER

SDRAM

INTERFACE

IOD

IOA

PM ADDRESS BUS

DM ADDRESS BUS

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

PM DATA BUS

BUS

CONNECT

(PX)

DATA BUS

MUX

40 DM DATA BUS

HOST PORT

DMA

DATA

IOP

REGISTERS

(MEMORY MAPPED)

CONTROLLER

FILE

(2 Rx, 2Tx)

40 BIT

BARREL

SHIFTER

SPORT 0

MULTIPLIER

ALU

CONTROL,

STATUS, TIMER

(I S)

(2 Rx, 2Tx)

DATA BUFFERS

SPORT 1

(I S)

I/O PROCESSOR

Figure 1. Functional Block Diagram

SHARC is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

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与ADSP-21065相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21065L	ADI	获取价格	DSP Microcomputer
ADSP-21065LCCA-240	ADI	获取价格	DSP Microcomputer
ADSP-21065LCCAZ-240	ROCHESTER	获取价格	32-BIT, 30 MHz, OTHER DSP, PBGA196, CHIP SCALE, MS-034AAE-1, BGA-196
ADSP-21065LCS-240	ADI	获取价格	DSP Microcomputer
ADSP-21065LCSZ-240	ADI	获取价格	DSP Microcomputer
ADSP-21065LCSZ-240	ROCHESTER	获取价格	32-BIT, 30 MHz, OTHER DSP, PQFP208, MS-029FA-1, MQFP-208
ADSP-21065LKCA-240	ADI	获取价格	DSP Microcomputer
ADSP-21065LKCA-264	ADI	获取价格	DSP Microcomputer
ADSP-21065LKCAZ-240	ROCHESTER	获取价格	32-BIT, 30 MHz, OTHER DSP, PBGA196, CHIP SCALE, MS-034AAE-1, BGA-196
ADSP-21065LKCAZ-240	ADI	获取价格	暂无描述

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