Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-21062LCS-160

ADSP-21062LCS-160

更新时间： 2024-11-26 22:31:27

品牌	Logo	应用领域
亚德诺 - ADI		微控制器和处理器外围集成电路数字信号处理器时钟
页数	文件大小	规格书
48页	368K
描述
ADSP-2106x SHARC DSP Microcomputer Family

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替代型号

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ADSP-2106x SHARC

DSP Microcomputer Family

ADSP-21062/ADSP-21062L

SUMMARY

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

High Performance Signal Processor for Communica-

tions, Graphics and Imaging Applications

Super Harvard Architecture

Four Independent Buses for Dual Data Fetch,

Instruction Fetch and Nonintrusive I/O

32-Bit IEEE Floating-Point Computation Units—

Multiplier, ALU, and Shifter

Dual-Ported On-Chip SRAM and Integrated I/O

Peripherals—A Complete System-On-A-Chip

Integrated Multiprocessing Features

240-Lead Thermally Enhanced MQFP Package

225-Ball Plastic Ball Grid Array (PBGA)

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats or 32-Bit Fixed-

Point Data Format

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel with

Dual Memory Read/Writes and Instruction Fetch

Multiply with Add and Subtract for Accelerated FFT

Butterfly Computation

KEY FEATURES

40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction

Execution

120 MFLOPS Peak, 80 MFLOPS Sustained Performance

Dual Data Address Generators with Modulo and Bit-

Reverse Addressing

2 Mbit On-Chip SRAM

Dual-Ported for Independent Access by Core Processor

and DMA

Off-Chip Memory Interfacing

4 Gigawords Addressable

Programmable Wait State Generation, Page-Mode

DRAM Support

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

DUAL-PORTED SRAM

CORE PROCESSOR

INSTRUCTION

TIMER

JTAG

TWO INDEPENDENT

CACHE

DUAL-PORTED BLOCKS

32 x 48-BIT

TEST &

EMULATION

PROCESSOR PORT

I/O PORT

DATA

ADDR

DATA

ADDR

DATA

ADDR

DATA

DAG2

DAG1

PROGRAM

SEQUENCER

8 x 4 x 24

8 x 4 x 32

EXTERNAL

PORT

IOD

IOA

PM ADDRESS BUS

ADDR BUS

MUX

DM ADDRESS BUS

MULTIPROCESSOR

INTERFACE

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DATA BUS

MUX

40/32

HOST PORT

DMA

DATA

FILE

IOP

REGISTERS

MEMORY MAPPED)

CONTROLLER

(

SERIAL PORTS

(2)

16 x 40-BIT

BARREL

SHIFTER

ALU

MULTIPLIER

CONTROL,

STATUS &

DATA BUFFERS

LINK PORTS

(6)

I/O PROCESSOR

Figure 1. ADSP-21062/ADSP-21062L Block Diagram

SHARC is a registered trademark of Analog Devices, Inc.

REV. C

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

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ADSP-21062LCS-160 替代型号

型号	品牌	替代类型	描述	数据表
ADSP-21062LCSZ-160	ADI	类似代替	SHARC Processor

与ADSP-21062LCS-160相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21062LCSZ-160	ADI	获取价格	SHARC Processor
ADSP-21062LKB-160	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062LKB-160	ROCHESTER	获取价格	48-BIT, 40 MHz, OTHER DSP, PBGA225, PLASTIC, MS-034AAJ-2, BGA-225
ADSP-21062LKBZ-160	ADI	获取价格	SHARC Processor
ADSP-21062LKS-133	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062LKS-160	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21062LKS-160	ROCHESTER	获取价格	48-BIT, 40 MHz, OTHER DSP, PQFP240, MS-029GA, MQFP-240
ADSP-21062LKSZ-133	ADI	获取价格	SHARC Processor
ADSP-21062LKSZ-133	ROCHESTER	获取价格	48-BIT, 33.33 MHz, OTHER DSP, PQFP240, ROHS COMPLIANT, MS-029GA, MQFP-240
ADSP-21062LKSZ-160	ADI	获取价格	SHARC Processor

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