Datasheet > ADS8608A8A-75

ADS8608A8A-75

更新时间： 2024-09-12 22:24:15

品牌	Logo	应用领域
威刚科技 - ADATA		动态存储器
页数	文件大小	规格书
8页	492K
描述
Synchronous DRAM(8M X 8 Bit X 4 Banks)

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ADS8608A8A-75 数据手册

A-Data

ADS8608A8A

8M x 8 Bit x 4 Banks

Synchronous DRAM

General Description

Features

•JEDEC standard LVTTL 3.3V power supply

•MRS Cycle with address key programs

The ADS8608A8A are four-bank Synchronous

DRAMs organized as 8,388,608 words x 8 bits x 4

banks.

-CAS Latency (2 & 3)

Synchronous design allows precise cycle control

with the use of system clock I/O transactions are

possible on every clock cycle.

Range of operating frequencies, programmable

burst length and programmable latencies allow the

same device to be useful for a variety of high

bandwidth high performance memory system

applications

-Burst Length (1,2,4,8,& full page)

-Burst Type (sequential & Interleave)

•4 banks operation

•All inputs are sampled at the positive edge of

the system clock

•Burst Read single write operation

•Auto & Self refresh

•DQM for masking

•8192 Refresh Cycles

•Package:54-pins 400 mil TSOP-Type II

Ordering Information.

Part No.

Frequency

133Mhz-333

133Mhz-222

Interface

Package

ADS8608A8A-75

ADS8608A8A-75A

Pin Assignment

LVTTL

400mil 54pin TSOPII

Vss

DQ7

DQ0

CCQ

Vss

DQ1

DQ6

SSQ

VCCQ

DQ2

DQ5

CCQ

VSSQ

DQ3

DQ4

SSQ

VCCQ

VSS

DQM

CLK

CKE

A12

A11

/WE

/CAS

/RAS

/CS

BS0

BS1

A10/AP

VSS

54-pin plastic TSOP II 400 mil

Rev 1.0 December, 2001

12 3 4 5 6 7 8

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