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ADS8285IRGCR

更新时间： 2024-11-26 14:47:39
品牌 Logo 应用领域
德州仪器 - TI 转换器
页数 文件大小 规格书
29页 789K
描述
8-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQCC64, 9 X 9 MM, PLASTIC, VQFN-64

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ADS8285IRGCR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：HVQCCN,
针数：64Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.84最大模拟输入电压：4.45 V
最小模拟输入电压：-3 V最长转换时间：0.65 µs
转换器类型：ADC, SUCCESSIVE APPROXIMATIONJESD-30 代码：S-PQCC-N64
JESD-609代码：e4长度：9 mm
最大线性误差 (EL)：0.0017%湿度敏感等级：3
标称负供电电压：-5 V模拟输入通道数量：8
位数：18功能数量：1
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出位码：BINARY
输出格式：PARALLEL, WORD封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified采样速率：1 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：1 mm
标称供电电压：5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：9 mmBase Number Matches：1

ADS8285IRGCR 数据手册

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SN75LVDS83B  
www.ti.com  
SLLS846A –MAY 2009–REVISED OCTOBER 2009  
FLATLINK™ TRANSMITTER  
Check for Samples: SN75LVDS83B  
1
FEATURES  
•
28 Data Channels Plus Clock In Low-Voltage  
TTL to 4 Data Channels Plus Clock Out  
Low-Voltage Differential  
2
•
•
•
LVDS Display Serdes Interfaces Directly to  
LCD Display Panels with Integrated LVDS  
•
•
Consumes Less Than 1mW When Disabled  
Package Options: 4.5mm x 7mm BGA, and  
8.1mm x 14mm TSSOP  
Selectable Rising or Falling Clock Edge  
Triggered Inputs  
1.8V up to 3.3V Tolerant Data Inputs to  
Connect Directly to Low-Power, Low-Voltage  
Application and Graphic Processors  
•
•
•
ESD: 5kV HBM  
Support Spread Spectrum Clocking (SSC)  
•
Transfer Rate up to 135Mpps (Mega Pixel Per  
Second); Pixel Clock Frequency Range 10MHz  
to 135MHz  
Compatible with all OMAP™2x, OMAP™3x,  
and DaVinci™ Application Processors  
•
•
Suited for Display Resolutions Ranging From  
HVGA up to HD With Low EMI  
APPLICATIONS  
•
•
•
LCD Display Panel Driver  
UMPC and Netbook PC  
Digital Picture Frame  
Operates From a Single 3.3V Supply and  
170mW (typ.) at 75MHz  
DESCRIPTION  
The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock  
synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These  
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair  
conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS  
receiver.  
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock  
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The  
frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and  
serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.  
The frequency of CLKOUT is the same as the input clock, CLKIN.  
Application  
processor  
SN75LVDS83B  
FlatLinkTM Transmitter  
(e.g. OMAPTM  
)
Package Options  
TSSOP: 8 x 14mm DGG  
BGA: 4.5 x 7mm  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
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