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ADS809 PDF预览

ADS809

更新时间: 2022-11-29 05:18:26
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20页 435K
描述
12-Bit, 80MHz Sampling ANALOG-TO-DIGITAL CONVERTER

ADS809 数据手册

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ADS809  
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SBAS170C NOVEMBER 2000 REVISED JANUARY 2003  
12-Bit, 80MHz Sampling  
ANALOG-TO-DIGITAL CONVERTER  
FEATURES  
DESCRIPTION  
DYNAMIC RANGE:  
The ADS809 is a high-dynamic range, 12-bit, 80MHz, pipelined  
Analog-to-Digital Converter (ADC). It includes a high-band-  
width linear track-and-hold that has a low jitter of only 0.5ps  
rms, leading to excellent Signal-to-Noise Ratio (SNR) perfor-  
mance. The clock input can accept a low-level differential sine  
wave or square wave signal down to 0.5Vp-p, further improv-  
ing the SNR performance. It also accepts a single-ended  
clock signal and has flexible threshold levels.  
SNR: 65dB at 10MHz fIN  
SFDR: 68dB at 10MHz fIN  
PREMIUM TRACK-AND-HOLD:  
Low Jitter: 0.5ps rms  
Differential or Single-Ended Inputs  
Selectable Full-Scale Input Range  
FLEXIBLE CLOCKING:  
The ADS809 has a 2Vp-p differential input range (1Vp-p 2  
inputs) for optimum signal-to-noise ratio. The differential  
operation gives the lowest even-order harmonic compo-  
nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be  
selected using the internal references, further optimizing  
Spurious-Free Dynamic Range (SFDR). Alternatively, a single-  
ended input range can be used by tying the IN input to the  
common-mode voltage if desired.  
Differential or Single-Ended  
Accepts Sine or Square Wave Clocking  
Down to 0.5Vp-p  
Variable Threshold Level  
APPLICATIONS  
The ADS809 also provides an over-range flag that indicates  
when the input signal has exceeded the converters full-scale  
range. This flag can also be used to reduce the gain of the  
front-end signal conditioning circuitry. It also employs digital  
error-correction techniques to provide excellent differential  
linearity for demanding imaging applications. The ADS809 is  
available in a small TQFP-48 PowerPADthermally-  
enhanced package.  
BASESTATION WIDEBAND RADIOS:  
CDMA, GSM, TDMA, 3G, AMPS, and NMT  
TEST INSTRUMENTATION  
CCD IMAGING  
PowerPAD is a registered trademark of Texas Instruments.  
+VS  
DV  
CLK  
ADS809  
Timing Circuitry  
CLK  
1Vp-p  
1Vp-p  
IN  
IN  
D0  
12-Bit  
Pipelined  
ADC Core  
Error  
Correction  
Logic  
3-State  
Outputs  
T&H  
D11  
CM  
(+2.5V)  
OVR  
Reference Ladder  
and Driver  
Reference and  
Mode Select  
REFT  
VREF SEL1 SEL2  
REFB  
OE VDRV  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2000-2003, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
www.ti.com  

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