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ADS808Y/250 PDF预览

ADS808Y/250

更新时间: 2024-02-27 00:25:23
品牌 Logo 应用领域
BB 转换器
页数 文件大小 规格书
19页 362K
描述
12-Bit, 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER

ADS808Y/250 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:HTQFP-48
针数:48Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:8.59Is Samacsys:N
最大模拟输入电压:2 V最小模拟输入电压:1 V
最长转换时间:1 µs转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQFP-G48JESD-609代码:e4
长度:7 mm最大线性误差 (EL):0.1709%
湿度敏感等级:3模拟输入通道数量:1
位数:12功能数量:1
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出位码:OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:PLASTIC/EPOXY
封装代码:HTFQFP封装等效代码:TQFP48,.35SQ
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified采样速率:70 MHz
采样并保持/跟踪并保持:TRACK座面最大高度:1.2 mm
子类别:Analog to Digital Converters标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7 mmBase Number Matches:1

ADS808Y/250 数据手册

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ADS808  
ADS808  
SBAS179C DECEMBER 2000 REVISED SEPTEMBER 2002  
12-Bit, 70MHz Sampling  
ANALOG-TO-DIGITAL CONVERTER  
FEATURES  
DESCRIPTION  
DYNAMIC RANGE:  
SNR: 64dB at 10MHz fIN  
SFDR: 68dB at 10MHz fIN  
The ADS808 is a high-dynamic range, 12-bit, 70MHz,  
pipelined Analog-to-Digital Converter (ADC). It includes a  
high-bandwidth linear track-and-hold that has a low jitter of  
only 0.25ps rms, leading to excellent SNR performance. The  
clock input can accept a low-level differential sine wave or  
square wave signal down to 0.5Vp-p, further improving the  
SNR performance. It also accepts a single-ended clock  
signal and has flexible threshold levels.  
PREMIUM TRACK-AND-HOLD:  
Low Jitter: 0.25ps rms  
Differential or Single-Ended Inputs  
Selectable Full-Scale Input Range  
FLEXIBLE CLOCKING:  
The ADS808 has a 2Vp-p differential input range (1Vp-p 2  
inputs) for optimum signal-to-noise ratio. The differential  
operation gives the lowest even-order harmonic compo-  
nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be  
selected using the internal references, further optimizing  
SFDR. Alternatively, a single-ended input range can be used  
by tying the IN input to the common-mode voltage, if desired.  
Differential or Single-Ended  
Accepts Sine or Square Wave Clocking  
Down to 0.5Vp-p  
Variable Threshold Level  
APPLICATIONS  
BASESTATION WIDEBAND RADIOS:  
The ADS808 also provides an over-range flag that indicates  
when the input signal has exceeded the converters full-scale  
range. This flag can also be used to reduce the gain of the  
front-end signal conditioning circuitry. It also employs digital  
error-correction techniques to provide excellent differential  
linearity for demanding imaging applications. The ADS808 is  
available in a small TQFP-48 PowerPADthermally en-  
hanced package.  
CDMA, GSM, TDMA, 3G, AMPS, and NMT  
TEST INSTRUMENTATION  
CCD IMAGING  
PowerPAD is a registered trademark of Texas Instruments.  
+VS  
DV  
CLK  
ADS808  
Timing Circuitry  
CLK  
1Vp-p  
1Vp-p  
IN  
IN  
D0  
12-Bit  
Pipelined  
ADC Core  
Error  
Correction  
Logic  
3-State  
Outputs  
T&H  
D11  
CM  
(+2.5V)  
OVR  
Reference Ladder  
and Driver  
Reference and  
Mode Select  
REFT  
VREF SEL1 SEL2  
REFB  
OE VDRV  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2000, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
www.ti.com  

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