A-Data
ADS6632A4A
512K x 32 Bit x 4 Banks
Synchronous DRAM
General Description
Features
•JEDEC standard LVTTL 3.3V power supply
•MRS Cycle with address key programs
The ADS6632A4A are four-bank Synchronous
DRAMs organized as 524,288 words x 32 bits x 4
banks,
-CAS Latency (2 & 3)
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
•4 banks operation
•All inputs are sampled at the positive edge of
the system clock
•Burst Read single write operation
•Auto & Self refresh
•4096 refresh cycle
•DQM for masking
•Package:86-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
200Mhz
183Mhz
166Mhz
Interface
Package
ADS6632A4A-5
LVTTL
LVTTL
LVTTL
400mil 86pin TSOPII
400mil 86pin TSOPII
400mil 86pin TSOPII
ADS6632A4A-5.5
ADS6632A4A-6
Pin Assignment
V
DD
V
S S
1
2
3
4
5
6
7
8
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
DQ0
DQ15
V
DDQ
DQ1
DQ2
V
S SQ
DQ14
DQ13
V
S S Q
DQ3
DQ4
V
DDQ
DQ12
DQ11
V
DDQ
DQ5
DQ6
V
S SQ
9
DQ10
DQ9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
V
S S Q
DQ7
NC
V
DDQ
DQ8
N C
V
DD
V
S S
DQM 0
WE
DQM 1
N C
N C
CLK
CKE
A9
CA S 1 8
RA S 1 9
CS
2 0
NC
21
22
23
24
25
26
27
28
29
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
39
4 0
4 1
4 2
4 3
A8
BA0
BA1
A10/AP
A0
A7
A6
A5
A4
A1
A3
A2
DQM 3
DQM 2
V
S S
V
DD
N C
DQ31
NC
DQ16
V
DDQ
V
SSQ
DQ30
DQ29
DQ17
DQ18
V
S S Q
V
DDQ
DQ28
DQ27
DQ19
DQ20
V
DDQ
V
SSQ
DQ26
DQ25
DQ21
DQ22
V
S S Q
V
DDQ
DQ24
DQ23
V
S S
V
DD
86-pin plastic TSOP II 400mil
Rev 1.0 April, 2001
1