Datasheet > ADS6608A4A-75

ADS6608A4A-75

更新时间： 2024-11-17 22:39:03

品牌	Logo	应用领域
威刚科技 - ADATA		动态存储器
页数	文件大小	规格书
8页	482K
描述
Synchronous DRAM(2M X 8 Bit X 4 Banks)

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ADS6608A4A-75 数据手册

A-Data

ADS6608A4A

2M x 8 Bit x 4 Banks

Synchronous DRAM

General Description

Features

•JEDEC standard LVTTL 3.3V power supply

•MRS Cycle with address key programs

The ADS6608A4A are four-bank Synchronous

DRAMs organized as 2,097,152 words x 8 bits x 4

banks.

-CAS Latency (2 & 3)

Synchronous design allows precise cycle control

with the use of system clock I/O transactions are

possible on every clock cycle.

Range of operating frequencies, programmable

burst length and programmable latencies allow the

same device to be useful for a variety of high

bandwidth high performance memory system

applications

-Burst Length (1,2,4,8,& full page)

-Burst Type (sequential & Interleave)

•4 banks operation

•All inputs are sampled at the positive edge of

the system clock

•Burst Read single write operation

•Auto & Self refresh

•4096 refresh cycle

•DQM for masking

•Package:54-pins 400 mil TSOP-Type II

Ordering Information.

Part No.

Frequency

133Mhz

Interface

LVTTL

Package

400mil 54pin TSOPII

ADS6608A4A-75

Pin Assignment

Vss

DQ0

DQ7

DDQ

Vss

DQ1

DQ6

SSQ

VDDQ

DQ2

DQ5

DDQ

VSSQ

DQ3

DQ4

SSQ

VDDQ

VSS

NC/RFU

DQM

/WE

/CAS

/RAS

/CS

BA0

BA1

A10/AP

CKE

A11

VSS

54-pin plastic TSOP II 400 mil

Rev 1 April, 2001

12 3 4 5 6 7 8

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