5秒后页面跳转
ADS6124IRHBTG4 PDF预览

ADS6124IRHBTG4

更新时间: 2024-01-27 05:00:43
品牌 Logo 应用领域
德州仪器 - TI 输出元件双倍数据速率
页数 文件大小 规格书
67页 2167K
描述
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6124IRHBTG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC32,.2SQ,20针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.44
最大模拟输入电压:2 V最小模拟输入电压:-2 V
转换器类型:ADC, PROPRIETARY METHODJESD-30 代码:S-PQCC-N32
JESD-609代码:e4长度:5 mm
最大线性误差 (EL):0.0488%湿度敏感等级:3
模拟输入通道数量:1位数:12
功能数量:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
输出位码:BINARY, OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式:PARALLEL, WORD
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
采样速率:105 MHz采样并保持/跟踪并保持:SAMPLE
座面最大高度:1 mm子类别:Analog to Digital Converters
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5 mm
Base Number Matches:1

ADS6124IRHBTG4 数据手册

 浏览型号ADS6124IRHBTG4的Datasheet PDF文件第2页浏览型号ADS6124IRHBTG4的Datasheet PDF文件第3页浏览型号ADS6124IRHBTG4的Datasheet PDF文件第4页浏览型号ADS6124IRHBTG4的Datasheet PDF文件第5页浏览型号ADS6124IRHBTG4的Datasheet PDF文件第6页浏览型号ADS6124IRHBTG4的Datasheet PDF文件第7页 
ADS6125, ADS6124  
ADS6123, ADS6122  
www.ti.com  
SLAS560AOCTOBER 2007REVISED MARCH 2008  
12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS  
1
FEATURES  
DESCRIPTION  
Maximum Sample Rate: 125 MSPS  
12-Bit Resolution with No Missing Codes  
ADS6125/ADS6124/ADS6123/ADS6122 (ADS612X)  
is a family of 12-bit A/D converters with sampling  
frequencies up to 125 MSPS. It combines high  
3.5 dB Coarse Gain and up to 6 dB  
Programmable Fine Gain for SNR/SFDR  
Trade-Off  
performance and low power consumption in  
a
compact 32 QFN package. Using an internal high  
bandwidth sample and hold and a low jitter clock  
buffer helps to achieve high SNR and high SFDR  
even at high input frequencies.  
Parallel CMOS and Double Data Rate (DDR)  
LVDS Output Options  
Supports Sine, LVCMOS, LVPECL, LVDS Clock  
Inputs and Clock Amplitude Down to 400 mVPP  
It features coarse and fine gain options that are used  
to improve SFDR performance at lower full-scale  
analog input ranges.  
Clock Duty Cycle Stabilizer  
Internal Reference with Support for External  
Reference  
The digital data outputs are either parallel CMOS or  
DDR LVDS (Double Data Rate). Several features  
exist to ease data capture such as — controls for  
output clock position and output buffer drive strength,  
and LVDS current and internal termination  
programmability.  
No External Decoupling Required for  
References  
Programmable Output Clock Position and  
Drive Strength to Ease Data Capture  
3.3 V Analog and 1.8 V to 3.3 V Digital Supply  
32-QFN Package (5 mm × 5 mm)  
The output interface type, gain, and other functions  
are programmed using a 3-wire serial interface.  
Alternatively, some of these functions are configured  
using dedicated parallel pins so that the device  
comes up in the desired state after power-up.  
Pin Compatible 12-Bit Family (ADS612X)  
APPLICATIONS  
Wireless Communications Infrastructure  
Software Defined Radio  
Power Amplifier Linearization  
802.16d/e  
Test and Measurement Instrumentation  
High Definition Video  
ADS612X includes internal references, while  
eliminating the traditional reference pins and  
associated external decoupling. External reference  
mode is also supported.  
The devices are specified over the industrial  
temperature range (–40°C to 85°C).  
Medical Imaging  
Radar Systems  
ADS612X Performance Summary  
ADS6125  
90  
ADS6124  
91  
ADS6123  
93  
ADS6122  
95  
Fin = 10 MHz (0 dB gain)  
Fin = 170 MHz (3.5 dB gain)  
Fin = 10 MHz (0 dB gain)  
Fin = 170 MHz (3.5 dB gain)  
Power, mW  
SFDR, dBc  
78  
82  
83  
84  
71.1  
67.6  
417  
71.3  
69.1  
374  
71.5  
69.2  
318  
71.6  
69.8  
285  
SINAD, dBFS  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2008, Texas Instruments Incorporated  

ADS6124IRHBTG4 替代型号

型号 品牌 替代类型 描述 数据表
ADS6123IRHBT TI

功能相似

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

与ADS6124IRHBTG4相关器件

型号 品牌 获取价格 描述 数据表
ADS6125 TI

获取价格

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS6125IRHB25 TI

获取价格

1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC32, 5 X 5 MM, GREEN, PLASTIC, QFN
ADS6125IRHBR TI

获取价格

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS6125IRHBRG4 TI

获取价格

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS6125IRHBT TI

获取价格

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS6125IRHBTG4 TI

获取价格

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS6128 TI

获取价格

14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs
ADS6128IRGZ25 TI

获取价格

1-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL/PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLAST
ADS6128IRGZR TI

获取价格

14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs
ADS6128IRGZRG4 TI

获取价格

14/12-Bit, 250/210 MSPS ADCs With DDR LVDS and Parallel CMOS Outputs