Datasheet > ADS5525_14

ADS5525_14

更新时间： 2024-09-18 02:58:35

品牌	Logo	应用领域
德州仪器 - TI		双倍数据速率输出元件
页数	文件大小	规格书
48页	807K
描述
12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

ADS5525_14 数据手册

ADS5525

www.ti.com

SLWS191–JULY 2006

12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

•

Power Amplifier Linearization

802.16d/e

Test and Measurement Instrumentation

High Definition Video

Medical Imaging

FEATURES

•

Maximum Sample Rate: 170 MSPS

12-Bit Resolution

No Missing Codes

Total Power Dissipation 1.1 W

Internal Sample and Hold

69.5-dBFS SNR at 70-MHz IF

82-dBc SFDR at 70-MHz IF, 0 dB gain

Radar Systems

DESCRIPTION

ADS5525 is a high performance 12-bit, 170-MSPS

A/D converter. It offers state-of-the art functionality

and performance using advanced techniques to

minimize board space. Using an internal sample and

hold and low jitter clock buffer, the ADC supports

both high SNR and high SFDR at high input

frequencies. It features programmable gain options

that can be used to improve SFDR performance at

lower full-scale analog input ranges.

Double Data Rate (DDR) LVDS and Parallel

CMOS Output Options

•

Programmable Gain up to 6 dB for SNR/SFDR

Trade-Off at High IF

Reduced Power Modes at Lower Sample

Rates

Supports input clock amplitude down to 400

mV_PP

In a compact 48-pin QFN, the device offers fully

differential LVDS DDR (Double Data Rate) interface

while parallel CMOS outputs can also be selected.

Flexible output clock position programmability is

available to ease capture and trade-off setup for hold

times. At lower sampling rates, the ADC can be

operated at scaled down power with no loss in

performance. ADS5525 includes an internal

reference, while eliminating the traditional reference

pins and associated external decoupling. The device

also supports an external reference mode.

•

Clock Duty Cycle Stabilizer

No External Reference Decoupling Required

Internal and External Reference Support

Programmable Output Clock position to ease

data capture

•

3.3-V Analog and Digital Supply

48-QFN Package (7 mm × 7 mm)

APPLICATIONS

•

The device is specified over the industrial

temperature range (-40°C to 85°C).

Wireless Communications Infrastructure

Software Defined Radio

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

12 3 4 5 6 7...48

中文翻译

下载PDF

与ADS5525_14相关器件

型号	品牌	获取价格	描述	数据表
ADS5525IRGZ25	TI	获取价格	1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN
ADS5525IRGZR	TI	获取价格	12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS5525IRGZRG4	TI	获取价格	12-bit, 170 MSPS ADC with User selectable DDR LVDS or Parallel CMOS outputs 48-VQFN -40 to
ADS5525IRGZT	TI	获取价格	12-BIT, 170 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS5525IRGZTG4	TI	获取价格	12-Bit, 170-MSPS Analog-to-Digital Converter (ADC) 48-VQFN -40 to 85
ADS5527	TI	获取价格	12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS5527_07	TI	获取价格	12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS5527IRGZ25	TI	获取价格	1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48, 7 X 7 MM, GREEN, PLASTIC, QFN
ADS5527IRGZR	TI	获取价格	12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
ADS5527IRGZRG4	TI	获取价格	12-BIT, 210 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

与ADS5525_14相关文章

摩尔斯微电子在美国约书亚树国家公园测试 Wi-Fi HaLow
2024-09-18

18
贸泽上架Tallysman TW5386智能GNSS天线
2024-09-18

16
SL74HC10N：高性能三输入与非门解析
2024-09-03

93
AIC1781A 电池充电控制器深度解析
2024-09-03

83

产品中心

服务支持

精选活动

关于我们

帮助中心

ADS5525_14

ADS5525_14 数据手册

与ADS5525_14相关器件

与ADS5525_14相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ADS5525_14

ADS5525_14 数据手册

与ADS5525_14相关器件

与ADS5525_14相关文章

您还可以找

您在本页遇到什么问题？