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ADS5263

更新时间： 2024-11-05 08:19:51
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德州仪器 - TI /
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69页 1566K
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Quad Channel 16-Bit, 100-MSPS High-SNR ADC 4 Vpp Full-scale Input

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ADS5263 数据手册

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ADS5263  
www.ti.com  
SLAS760A –MAY 2011–REVISED AUGUST 2011  
Quad Channel 16-Bit, 100-MSPS High-SNR ADC  
Check for Samples: ADS5263  
1
FEATURES  
APPLICATIONS  
•
•
Maximum Sample Rate: 100 MSPS  
Programmable Device Resolution  
•
•
•
Medical Imaging – MRI  
Spectroscopy  
–
–
Quad-Channel, 16-Bit, High-SNR Mode  
Quad-Channel, 14-Bit, Low-Power Mode  
CCD Imaging  
•
•
16-Bit High-SNR Mode  
–
1.4 W Total Power at 100 MSPS  
355 mW / Channel  
–
DESCRIPTION  
–
–
4 Vpp Full-scale Input  
Using CMOS process technology and innovative  
circuit techniques, the ADS5263 is designed to  
operate at low power and give very high SNR  
performance with a 4-Vpp full-scale input. Using a  
low-noise 16-bit front-end stage followed by a 14-bit  
ADC, the device gives 85-dBFS SNR up to 10 MHz  
and better than 80-dBFS SNR up to 30 MHz.  
85-dBFS SNR at fin = 3 MHz, 100 MSPS  
14-Bit Low-Power Mode  
–
785 mW Total Power at 100 MSPS  
195 mW/Channel  
–
–
–
–
2-Vpp Full-Scale Input  
The device also has a 14-bit low power mode, where  
it operates as a quad-channel 14-bit ADC. The 16-bit  
front-end stage is powered down and the part  
consumes almost half the power, compared to the  
16-bit mode. The 14-bit mode supports a 2-Vpp  
full-scale input signal, with typical 74-dBFS SNR. The  
ADS5263 can be dynamically switched between the  
two resolution modes. This allows systems to use the  
same part in a high-resolution, high-power mode or a  
low-resolution, low-power mode.  
74-dBFS SNR at fin = 10 MHz  
Integrated Clamp (for interfacing to CCD  
sensors)  
•
•
Low-Frequency Noise Suppression  
Digital Processing Block  
–
–
–
Programmable FIR Decimation Filters  
Programmable Digital Gain: 0 dB to 12 dB  
2- or 4-Channel Averaging  
•
•
Programmable Mapping Between ADC Input  
Channels and LVDS Output Pins—Eases  
Board Design  
The ADS5263 has a digital processing block that  
integrates several commonly used digital functions,  
such as digital gain (up to 12 dB). It includes a digital  
filter module that has built-in decimation filters (with  
low-pass, high-pass and band-pass characteristics).  
The decimation rate is also programmable (by 2, by  
4, or by 8). This makes it very useful for narrow-band  
applications, where the filters can be used to improve  
SNR and knock-off harmonics, while at the same time  
reducing the output data rate.  
Variety of Test Patterns to Verify Data Capture  
by FPGA/Receiver  
•
•
•
•
•
Serialized LVDS Outputs  
Internal and External References  
3.3-V Analog Supply  
1.8-V Digital Supply  
The device includes an averaging mode where two  
channels (or even four channels) can be averaged to  
Recovers From 6-dB Overload Within 1 Clock  
Cycle  
improve SNR.  
A
very unique feature is the  
•
Package:  
programmable mapper module that allows flexible  
mapping between the input channels and the LVDS  
output pins. This helps to greatly reduce the  
complexity of LVDS output routing and can potentially  
result in cheaper system boards by reducing the  
number of PCB layers.  
–
–
9-mm × 9-mm 64-Pin QFN  
Non-magnetic package option for MRI  
systems  
•
CMOS Technology  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011, Texas Instruments Incorporated  
 
 
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ADS5263 替代型号

型号 品牌 替代类型 描述 数据表
ADS5296A TI

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