ADS41B29
ADS41B49
www.ti.com
SBAS486E – NOVEMBER 2009–REVISED JULY 2012
14-/12-Bit, 250MSPS, Ultralow-Power ADC
with Analog Buffers
Check for Samples: ADS41B29, ADS41B49
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FEATURES
DESCRIPTION
The ADS41B29/B49 are members of the ultralow-
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ADS41B49: 14-Bit, 250MSPS
ADS41B29: 12-Bit, 250MSPS
power ADS4xxx analog-to-digital converter (ADC)
family, featuring integrated analog input buffers.
These devices use innovative design techniques to
achieve high dynamic performance, while consuming
extremely low power. The analog input pins have
buffers, with benefits of constant performance and
input impedance across a wide frequency range. The
devices are well-suited for multi-carrier, wide
bandwidth communications applications such as PA
linearization.
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Integrated High-Impedance
Analog Input Buffer:
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Input Capacitance: 2pF
200MHz Input Resistance: 3kΩ
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Maximum Sample Rate: 250MSPS
Ultralow Power:
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1.8V Analog Power: 180mW
3.3V Buffer Power: 96mW
The ADS41B49/29 have features such as digital gain
and offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
I/O Power: 135mW (DDR LVDS)
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High Dynamic Performance:
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SNR: 69dBFS at 170MHz
SFDR: 82.5dBc at 170MHz
Output Interface:
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Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
The devices support both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500MBPS)
makes it possible to use low-cost field-programmable
gate array (FPGA)-based receivers. The devices
have a low-swing LVDS mode that can be used to
further reduce the power consumption. The strength
of the LVDS output buffers can also be increased to
support 50Ω differential termination.
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Standard Swing: 350mV
Low Swing: 200mV
Default Strength: 100Ω Termination
2x Strength: 50Ω Termination
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1.8V Parallel CMOS Interface Also
Supported
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Programmable Gain for SNR/SFDR Trade-Off
DC Offset Correction
The devices are available in a compact QFN-48
package and are specified over the industrial
temperature range (–40°C to +85°C).
Supports Low Input Clock Amplitude
Package: QFN-48 (7mm × 7mm)
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2012, Texas Instruments Incorporated