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ADS2806 PDF预览

ADS2806

更新时间: 2024-10-31 22:39:03
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BB 转换器
页数 文件大小 规格书
19页 376K
描述
Dual, 12-Bit, 32MHz Sampling ANALOG-TO-DIGITAL CONVERTER

ADS2806 数据手册

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ADS2806  
ADS2806  
SBAS178B – DECEMBER 2000 – REVISED MAY 2002  
Dual, 12-Bit, 32MHz Sampling  
ANALOG-TO-DIGITAL CONVERTER  
FEATURES  
APPLICATIONS  
SPURIOUS-FREE DYNAMIC RANGE:  
COMMUNICATIONS IF PROCESSING  
COMMUNICATIONS BASESTATIONS  
TEST EQUIPMENT  
73dB at 10MHz fIN  
HIGH SNR: 67dB (2Vp-p), 69dB (3Vp-p)  
INTERNAL OR EXTERNAL REFERENCE  
LOW DLE: ±0.4LSB  
MEDICAL IMAGING  
VIDEO DIGITIZING  
FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p  
TQFP-64 POWER PACKAGE  
CCD DIGITIZING  
reference can be disabled allowing low drive, external refer-  
ences to be used for improved tracking in multichannel systems.  
DESCRIPTION  
The ADS2806 is a dual, high-speed, high dynamic range,  
12-bit pipelined Analog-to-Digital Converter (ADC). This con-  
verter includes a high-bandwidth track-and-hold that gives  
excellent spurious performance up to and beyond the Nyquist  
rate. The differential nature of this track-and-hold and ADC  
circuitry minimizes even-order harmonics and gives excel-  
lent common-mode noise immunity. The track-and-hold can  
also be operated single-ended.  
The ADS2806 provides an over-range indicator flag to  
indicate an input signal that exceeds the full-scale input  
range of the converter. This flag can be used to reduce the  
gain of front end gain control circuitry. There is also an  
output enable pin to allow for multiplexing and testability on  
a PC board.  
The ADS2806 employs digital error correction techniques to  
provide excellent differential linearity for demanding imag-  
ing applications. The ADS2806 is available in a TQFP-64  
power package.  
The ADS2806 provides for setting the full-scale range of the  
converter without any external reference circuitry. The internal  
+VS  
OEA OVRA  
ADS2806  
D12A  
VIN  
INA  
12-Bit  
Pipelined  
A/D  
Error  
Correction  
Logic  
3-State  
Outputs  
T&H  
D1A  
INA  
(Opt.)  
INT/EXT  
FSSEL  
Internal  
Reference  
Timing  
Circuitry  
CLK  
VIN  
D12B  
INB  
12-Bit  
Pipelined  
A/D  
Error  
Correction  
Logic  
3-State  
Outputs  
T&H  
D1B  
INB  
(Opt.)  
CM  
OEB  
OVRB  
Optional External  
Reference  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2000, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
www.ti.com  

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