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ADN4667

更新时间: 2024-11-27 03:17:51
品牌 Logo 应用领域
亚德诺 - ADI 驱动器
页数 文件大小 规格书
12页 224K
描述
3 V LVDS Quad CMOS Differential Line Driver

ADN4667 数据手册

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3 V LVDS Quad CMOS  
Differential Line Driver  
ADN4667  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
V
CC  
15 kV ESD protection on output pins  
400 Mbps (200 MHz) switching rates  
Flow-through pinout simplifies PCB layout  
300 ps typical differential skew  
400 ps maximum differential skew  
1.7 ns maximum propagation delay  
3.3 V power supply  
ADN4667  
D
D
OUT1+  
OUT1–  
D1  
D2  
D3  
D4  
D
D
D
D
IN1  
IN2  
IN3  
IN4  
D
D
OUT2+  
OUT2–  
D
D
OUT3+  
OUT3–  
310 mV differential signaling  
Low power dissipation (10 mW typical)  
Interoperable with existing 5 V LVDS receivers  
High impedance on LVDS outputs on power-down  
Conforms to TIA/EIA-644 LVDS standard  
Industrial operating temperature range: −40°C to +85°C  
Available in low profile TSSOP package  
D
D
OUT4+  
OUT4–  
EN  
EN  
GND  
Figure 1.  
APPLICATIONS  
Backplane data transmission  
Cable data transmission  
Clock distribution  
GENERAL DESCRIPTION  
The ADN4667 is a quad, CMOS, low voltage differential  
signaling (LVDS) line driver offering data rates of over  
400 Mbps (200 MHz) and ultralow power consumption.  
It features a flow-through pinout for easy PCB layout and  
separation of input and output signals.  
The ADN4667 also offers active high and active low enable/  
EN  
drivers and turn off the current outputs in the disabled state to  
reduce the quiescent power consumption to typically 10 mW.  
disable inputs (EN and  
). These inputs control all four  
The ADN4667 and a companion LVDS receiver offer a new  
solution to high speed, point-to-point data transmission, and a  
low power alternative to emitter-coupled logic (ECL) or positive  
emitter-coupled logic (PECL).  
The device accepts low voltage TTL/CMOS logic signals and  
converts them to a differential current output of typically ±±.1 mA  
for driving a transmission medium such as a twisted pair cable.  
The transmitted signal develops a differential voltage of typi-  
cally ±±10 mV across a termination resistor at the receiving end.  
This is converted back to a TTL/CMOS logic level by an LVDS  
receiver.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
 
 
 

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