3 V, LVDS, Quad CMOS
Differential Line Receiver
ADN4666
FEATURES
FUNꢁTIONAL BLOꢁK DIAGRAM
8 kꢀ ESD IEꢁ 61000-4-2 contact discharge on receiver input pins
400 Mbps (200 MHz) switching rates
100 ps channel-to-channel skew (typical)
100 ps differential skew (typical)
V
ADN4666
CC
R
R
R
IN1–
IN4–
R
IN1+
IN4+
R4
R1
3.3 ns propagation delay (maximum)
3.3 ꢀ power supply
R
R
OUT1
EN
OUT4
High impedance outputs on power-down
Low power design (10 mW quiescent typical)
Interoperable with existing 5 ꢀ LꢀDS drivers
Accepts small swing (350 mꢀ typical) differential
input signal levels
EN
R
R
OUT2
OUT3
R3
R2
Supports open, short, and terminated input fail-safe
ꢁonforms to TIA/EIA-644 LꢀDS standard
Industrial operating temperature range of −40°ꢁ to +85°ꢁ
Available in surface-mount SOIꢁ package and low profile
TSSOP package
R
R
R
IN2+
IN3+
R
IN2–
IN3–
GND
Figure 1.
APPLIꢁATIONS
Point-to-point data transmission
Multidrop buses
ꢁlock distribution networks
Backplane receivers
GENERAL DESꢁRIPTION
The ADN4666 is a quad-channel, CMOS low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
disable the receivers and switch the outputs to a high impedance
state. Consequently, the outputs of one or more ADN4666
devices can be multiplexed together to reduce the quiescent
power consumption to 10 mW typical.
The device accepts low voltage (350 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.
The ADN4666 and its companion driver, the ADN4665, offer
a new solution to high speed, point-to-point data transmission
and offer a low power alternative to emitter-coupled logic (ECL)
or positive emitter-coupled logic (PECL).
The ADN4666 also offers active high and active low enable/disable
EN
inputs (EN and
) that control all four receivers. These inputs
Rev. 0
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